High-level transformations for minimizing syntactic variances
DAC '93 Proceedings of the 30th international Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
High-Level Synthesis for Real-Time Digital Signal Processing
High-Level Synthesis for Real-Time Digital Signal Processing
The Synthesis Approach to Digital System Design
The Synthesis Approach to Digital System Design
The VERILOG Hardware Description Language
The VERILOG Hardware Description Language
High-Level VLSI Synthesis
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
HardwareC -- A Language for Hardware Design (Version 2.0)
HardwareC -- A Language for Hardware Design (Version 2.0)
On the use of VHDL-based behavioral synthesis for telecom ASIC design
ISSS '95 Proceedings of the 8th international symposium on System synthesis
From VHDL to efficient and first-time-right designs: a formal approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
High-level synthesis for testability: a survey and perspective
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Combined control flow dominated and data flow dominated high-level synthesis
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Analysis of different protocol description styles in VHDL for high-level synthesis
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Comparing RTL and behavioral design methodologies in the case of a 2M-transistor ATM shaper
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
On the fundamental limitations of transformational design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Introduction to the Scheduling Problem
IEEE Design & Test
Design Methodology for a Large Communication Chip
IEEE Design & Test
High-Level Synthesis of Recoverable Microarchitectures
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Object oriented prototyping at the system level: an image reconstruction application example
RSP '96 Proceedings of the 7th IEEE International Workshop on Rapid System Prototyping (RSP '96)
Optimal Recovery Point Insertion for High-Level Synthesis of Recoverable Microarchitectures
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Modeling and formal verification of embedded systems based on a Petri net representation
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
A Formal Verification Method of Scheduling in High-level Synthesis
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Beyond event handlers: programming wireless sensors with attributed state machines
IPSN '05 Proceedings of the 4th international symposium on Information processing in sensor networks
Hand-in-hand verification of high-level synthesis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Verification method of dataflow algorithms in high-level synthesis
Journal of Systems and Software
An area optimized reconfigurable encryptor for AES-Rijndael
Proceedings of the conference on Design, automation and test in Europe
EURASIP Journal on Embedded Systems
Automated formal verification of scheduling with speculative code motions
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Towards a holistic CAD platform for nanotechnologies
Microelectronics Journal
Journal of Signal Processing Systems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Semantics and verification of a language for modelling hardware architectures
Formal methods and hybrid real-time systems
Coverage driven high-level test generation using a polynomial model of sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Guided gate-level ATPG for sequential circuits using a high-level test generation approach
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Combining several paradigms for circuit validation and verification
CASSIS'04 Proceedings of the 2004 international conference on Construction and Analysis of Safe, Secure, and Interoperable Smart Devices
ESL Design and Verification: A Prescription for Electronic System Level Methodology
ESL Design and Verification: A Prescription for Electronic System Level Methodology
Hardware design space exploration using HercuLeS HLS
Proceedings of the 17th Panhellenic Conference on Informatics
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The basic problem of high-level synthesis is the mapping of a behavioral description of a digital system into an RTL design consisting of a data path and a control unit. The authors introduce the FSMD model, which forms the basis for synthesis. They discuss the main considerations in a high-level synthesis environment: the input description language, the internal representation, and the main synthesis tasks-allocation, scheduling, and binding. They conclude with some problems that must be solved to make high-level synthesis a widely accepted methodology.