ACM SIGPLAN Notices
Introduction to High-Level Synthesis
IEEE Design & Test
Simple Generation of Static Single-Assignment Form
CC '00 Proceedings of the 9th International Conference on Compiler Construction
RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability
RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability
High-Level Synthesis: from Algorithm to Digital Circuit
High-Level Synthesis: from Algorithm to Digital Circuit
Automated Synthesis of FSMD-Based Accelerators for Hardware Compilation
ASAP '12 Proceedings of the 2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors
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HercuLeS is an extensible high-level synthesis (HLS) environment. It removes significant human effort by automatically mapping algorithms to hardware, providing a valuable design assist to software-oriented developers. To enable accessibility and easiness of hardware design space exploration (DSE), HercuLeS overcomes limitations of known work: non-standard source languages, insufficient representations, maintenance difficulties, necessity of code templates, lack of usage paradigms and vendor-dependence. Specific aspects that are highlighted in this manuscript are: a) the in-nerworkings of the HercuLeS hardware compilation engine, b) manipulation of SSA (Static Single Assignment) form, c) automatic third-party IP integration, d) backend C code generation for compiled simulation, and e) an exemplary case of DSE. HercuLeS enables efficient hardware generation that can closely match the quality of results of a manually-developed implementation with much reduced human effort and time requirements.