Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
VLSI array processors
Behavior-preserving transformations for high-level synthesis
Proceedings of the Mathematical Sciences Institute workshop on Hardware specification, verification and synthesis: mathematical aspects
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Software engineering (3rd ed.): a practitioner's approach
Software engineering (3rd ed.): a practitioner's approach
Introducing structure into behavioural descriptions obtained from timing diagram specifications
EUROMICRO 93 Nineteenth EUROMICRO symposium on microprocessing and microprogramming on Open system design : hardware, software and applications: hardware, software and applications
High-level transformations for minimizing syntactic variances
DAC '93 Proceedings of the 30th international Design Automation Conference
Critical path minimization using retiming and algebraic speed-up
DAC '93 Proceedings of the 30th international Design Automation Conference
Formal analysis of correctness of behavioral transformations
Formal Methods in System Design
The U.S. HDTV standard—the grand alliance
IEEE Spectrum
Jumping the technology s-curve
IEEE Spectrum
Transformations on dependency graphs: formal specification and efficient mechanical verification
Transformations on dependency graphs: formal specification and efficient mechanical verification
A specification invariant technique for operation cost minimisation in flow-graphs
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
The system architect's workbench
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Program Improvement by Source-to-Source Transformation
Journal of the ACM (JACM)
Anatomy of a Silicon Compiler
Synthesis of Digital Design from Recursive Equations
Synthesis of Digital Design from Recursive Equations
Introduction to High-Level Synthesis
IEEE Design & Test
Introduction to the Scheduling Problem
IEEE Design & Test
Effective Theorem Proving for Hardware Verification
TPCD '94 Proceedings of the Second International Conference on Theorem Provers in Circuit Design - Theory, Practice and Experience
An Integration of Model Checking with Automated Proof Checking
Proceedings of the 7th International Conference on Computer Aided Verification
Arbitrary hardware software trade-offs
RSP '95 Proceedings of the Sixth IEEE International Workshop on Rapid System Prototyping (RSP'95)
PHIDEO: a silicon compiler for high speed algorithms
EURO-DAC '91 Proceedings of the conference on European design automation
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the fundamental limitations of transformational design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Formal Methods in System Design
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In this article we provide a practical transformational approach to the synthesis of correct synchronous digital hardware designs from high-level specifications. We do this while taking into account the complete life cycle of a design from early prototype to full custom implementation. Besides time-to-market, both flexibility with respect to target architecture and efficiency issues are addressed by the methodology. The utilization of user-selected behavior-preserving transformation steps ensures first-time-right design while exploiting the experience, flexibility, and creativity of the designer.To ensure that design transformations are indeed behavior-preserving a novel mechanized approach to the specification and verification of design transformations on control data flow graphs which is independent of a specific behavioral model or graph size has been developed.As a demonstration of an industrial application we use a video processing algorithm needed for the conversion from a line-interlaced to progressively scanned video format. Both a video signal processor-based prototype implementation as well as a very efficient full custom implementation are developed starting from a single high-level behavioral specification of the algorithm in VHDL. Results are compared with those previously obtained using different tools and methodologies.