Formal Verification for Fault-Tolerant Architectures: Prolegomena to the Design of PVS
IEEE Transactions on Software Engineering
From VHDL to efficient and first-time-right designs: a formal approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Mechanical Verification of Adder Circuits using Rewrite RuleLaboratory
Formal Methods in System Design
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 38th annual Design Automation Conference
Multiway Decision Graphs for Automated Hardware Verification
Formal Methods in System Design
Modular Verification of SRT Division
Formal Methods in System Design
A Proof of Correctness of a Processor Implementing Tomasulo's Algorithm without a Reorder Buffer
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
WIFT '95 Proceedings of the 1st Workshop on Industrial-Strength Formal Specification Techniques
Systematic Formal Verification of Interpreters
ICFEM '97 Proceedings of the 1st International Conference on Formal Engineering Methods
Verification of design decisions in ForSyDe
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
On deriving equivalent architecture model from system specification
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
IEEE Transactions on Computers
LCF-Style Propositional Simplification with BDDs and SAT Solvers
TPHOLs '08 Proceedings of the 21st International Conference on Theorem Proving in Higher Order Logics
Metareasoning for multi-agent epistemic logics
CLIMA'04 Proceedings of the 5th international conference on Computational Logic in Multi-Agent Systems
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