Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Formal hardware verification by symbolic ternary trajectory evaluation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Model checking and abstraction
POPL '92 Proceedings of the 19th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Reducing BDD size by exploiting functional dependencies
DAC '93 Proceedings of the 30th international Design Automation Conference
Model checking, abstraction, and compositional verification
Model checking, abstraction, and compositional verification
FM8501: a verified microprocessor
FM8501: a verified microprocessor
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A new method for verifying sequential circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Expressing interesting properties of programs in propositional temporal logic
POPL '86 Proceedings of the 13th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Automated Verification of Behavioral Equivalence for Microprocessors
IEEE Transactions on Computers
RTL Design Verification by Making Use of Datapath Information
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Effective Theorem Proving for Hardware Verification
TPCD '94 Proceedings of the Second International Conference on Theorem Provers in Circuit Design - Theory, Practice and Experience
Comparing Generic State Machines
CAV '91 Proceedings of the 3rd International Workshop on Computer Aided Verification
Efficient Model Checking by Automated Ordering of Transition Relation Partitions
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Analysis of Discrete Event Coordination
Stepwise Refinement of Distributed Systems, Models, Formalisms, Correctness, REX Workshop
Automated High-level Verification Against Clocked Algorithmic Specifications
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
Partitioning transition relations efficiently and automatically
GLSVLSI '95 Proceedings of the Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Formal hardware verification by integrating HOL and MDG
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Comparing HOL and MDG: a case study on the verification of an ATM switch fabric
Nordic Journal of Computing
Detecting Multiple Classes of User Errors
EHCI '01 Proceedings of the 8th IFIP International Conference on Engineering for Human-Computer Interaction
Three Approaches to Hardware Verification: HOL, MDG and VIS Compared
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Model Reductions and a Case Study
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Formal Verification of a SONET Telecom System Block
ICFEM '02 Proceedings of the 4th International Conference on Formal Engineering Methods: Formal Methods and Software Engineering
Enabling Hardware Verification through Design Changes
ICFEM '02 Proceedings of the 4th International Conference on Formal Engineering Methods: Formal Methods and Software Engineering
Importing MDG Verification Results into HOL
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
Symbolic Simulation of Microprocessor Models using Type Classes in Haskell
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Hierarchical Verification Using an MDG-HOL Hybrid Tool
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Formally Linking MDG and HOL Based on a Verified MDG System
IFM '02 Proceedings of the Third International Conference on Integrated Formal Methods
Model Checking Object-Z Using ASM
IFM '02 Proceedings of the Third International Conference on Integrated Formal Methods
Language emptiness checking using MDGs
Proceedings of the 13th ACM Great Lakes symposium on VLSI
On the non-termination of MDG-based abstract state enumeration
Theoretical Computer Science
Data structures for symbolic multi-valued model-checking
Formal Methods in System Design
Hybrid verification integrating HOL theorem proving with MDG model checking
Microelectronics Journal
Providing a formal linkage between MDG and HOL
Formal Methods in System Design
Reachability analysis using multiway decision graphs in the HOL theorem prover
Proceedings of the 2008 ACM symposium on Applied computing
Formal verification of ASMs using MDGs
Journal of Systems Architecture: the EUROMICRO Journal
A New Approach for the Construction of Multiway Decision Graphs
Proceedings of the 5th international colloquium on Theoretical Aspects of Computing
ATVA '08 Proceedings of the 6th International Symposium on Automated Technology for Verification and Analysis
LCF-style Platform based on Multiway Decision Graphs
Electronic Notes in Theoretical Computer Science (ENTCS)
An abstract reachability approach by combining HOL induction and multiway decision graphs
Journal of Computer Science and Technology
Interfacing ASM with the MDG tool
ASM'03 Proceedings of the abstract state machines 10th international conference on Advances in theory and practice
Static slicing-based pre-reduction technique for MDG model-checker
IIT'09 Proceedings of the 6th international conference on Innovations in information technology
NuMDG: a new tool for multiway decision graphs construction
Journal of Computer Science and Technology - Special issue on natural language processing
MDG-SAT: an automated methodology for efficient safety checking
International Journal of Critical Computer-Based Systems
High level reduction technique for multiway decision graphs based model checking
VECoS'07 Proceedings of the First international conference on Verification and Evaluation of Computer and Communication Systems
Multiway decision graphs reduction approach based on the HOL theorem prover
VECoS'08 Proceedings of the Second international conference on Verification and Evaluation of Computer and Communication Systems
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Traditional ROBDD-based methods of automated verificationsuffer from the drawback that they require a binary representation of thecircuit. To overcome this limitation we propose a broader class ofdecision graphs, called {\em Multiway Decision Graphs} (MDGs), of whichROBDDs are a special case. With MDGs, a data value is represented by asingle variable of abstract type, rather than by 32 or 64 booleanvariables, and a data operation is represented by an uninterpretedfunction symbol. MDGs are thus much more compact than ROBDDs, and thisgreatly increases the range of circuits that can be verified. We givealgorithms for MDG manipulation, and for implicit state enumeration usingMDGs. We have implemented an MDG package and provide experimental results.