Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Programming in Prolog
ML for the working programmer
Introduction to HOL: a theorem proving environment for higher order logic
Introduction to HOL: a theorem proving environment for higher order logic
Formal Methods in System Design - Special issue on symmetry in automatic verification
From LCF to HOL: a short history
Proof, language, and interaction
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Introduction to Formal Hardware Verification: Methods and Tools for Designing Correct Circuits and Systems
Multiway Decision Graphs for Automated Hardware Verification
Formal Methods in System Design
Compositional Reasoning in Model Checking
COMPOS'97 Revised Lectures from the International Symposium on Compositionality: The Significant Difference
Verification of Infinite State Systems by Compositional Model Checking
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
InVeST: A Tool for the Verification of Invariants
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Syntactic Program Transformations for Automatic Abstraction
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
A Stubborn Attack On State Explosion
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Reachability analysis using multiway decision graphs in the HOL theorem prover
Proceedings of the 2008 ACM symposium on Applied computing
High level reduction technique for multiway decision graphs based model checking
VECoS'07 Proceedings of the First international conference on Verification and Evaluation of Computer and Communication Systems
Modeling and formal verification of the Fairisle ATM switch fabric using MDGs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Multiway Decision Graphs (MDGs) subsume Binary Decision Diagrams (BDDs) by representing formulae which are suitable for first-order model checking able to handle large datapath circuits. In this paper, we propose a reduction approach to improve MDGs model checking. We use a reduction platform based on combining MDGs with the rewriting engine of the HOL theorem prover. The idea is to prune the transition relation of the design using pre-proved theorems and lemmas from the specification given at system level. Then, the actual proof of temporal MDG formulae will be achieved by the MDGs model checker.