Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Programming in Prolog (3rd ed.)
Programming in Prolog (3rd ed.)
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
A hybrid verification approach: getting deep into the design
Proceedings of the 39th annual Design Automation Conference
Multiway Decision Graphs for Automated Hardware Verification
Formal Methods in System Design
Formal Verification of the Island Tunnel Controller Using Multiway Decision Graphs
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
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CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
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On the non-termination of MDG-based abstract state enumeration
Theoretical Computer Science
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Static slicing-based pre-reduction technique for MDG model-checker
IIT'09 Proceedings of the 6th international conference on Innovations in information technology
Multiway decision graphs reduction approach based on the HOL theorem prover
VECoS'08 Proceedings of the Second international conference on Verification and Evaluation of Computer and Communication Systems
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Multiway Decision Graphs (MDGs) represent and manipulate a subset of first-order logic formulae suitable for model checking of large data path circuits. Due to the presence of abstract variables, existing reduction algorithms that is defined on symbolic model checking with BDD cannot be used with MDG. In this paper we propose a technique to construct a reduced MDG model for circuits described at algorithmic level in VHDL. The simplified model can be obtained using a high level symbolic simulator called TheoSim, and by running an appropriate symbolic simulation patterns. Then, the actual proof of a temporal MDG formula will be generated. We support our reduction technique by experimental results executed on benchmark properties.