Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The program dependence graph and its use in optimization
ACM Transactions on Programming Languages and Systems (TOPLAS)
Checking that finite state concurrent programs satisfy their linear specification
POPL '85 Proceedings of the 12th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Introduction to Formal Hardware Verification: Methods and Tools for Designing Correct Circuits and Systems
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Multiway Decision Graphs for Automated Hardware Verification
Formal Methods in System Design
Minimizing Interacting Finite State Machines: A Compositional Approach to Language to Containment
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Model checking for a first-order temporal logic using multiway decision graphs
Model checking for a first-order temporal logic using multiway decision graphs
Improved verification of hardware designs through antecedent conditioned slicing
International Journal on Software Tools for Technology Transfer (STTT) - Special Section on Advances in Automated Verification of Critical Systems
High level reduction technique for multiway decision graphs based model checking
VECoS'07 Proceedings of the First international conference on Verification and Evaluation of Computer and Communication Systems
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The hardware designs that are described at the register transfer level (RTL) have become more complex and difficult to debug. Therefore, using Multiway Decision Graphs (MDG), the same designs can be defined into a more abstract environment. However, to avoid the state explosion problem, the MDG-based designs still need to be reduced. Moreover, all the backward reduction algorithms cannot be used in MDG, due to the presence of abstract state variables. In this paper, we study this problem and propose a new reduction technique, called static slicing pre-reduction technique (SSPrMDG), in order to deal with the MDG-based designs. The main feature of our SSPr-MDG is to construct a reduced transition relation (Tr) using circuit dependency graph (CCDG). Our results, along with the case study, indicate the practical merits of the SSPr-MDG in terms of processing time, graph size, and memory capacity.