Static slicing-based pre-reduction technique for MDG model-checker
IIT'09 Proceedings of the 6th international conference on Innovations in information technology
Checking and deriving module paths in Verilog cell library descriptions
Proceedings of the Conference on Design, Automation and Test in Europe
PETRI NETS'12 Proceedings of the 33rd international conference on Application and Theory of Petri Nets
Using static analysis for coverage extraction fromemulation/prototyping platforms
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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Static slicing has shown itself to be a valuable tool, facilitating the verification of hardware designs. In this paper, we present a sharpened notion, antecedent conditioned slicing that provides a more effective abstraction for reducing the size of the state space. In antecedent conditioned slicing, extra information from the antecedent is used to permit greater pruning of the state space. In a previous version of this paper, we applied antecedent conditioned slicing to safety properties of the form G(antecedent ⇒ consequent) where antecedent and consequent were written in propositional logic. In this paper, we use antecedent conditioned slicing to handle safety and bounded liveness property specifications written in linear time temporal logic. We present a theoretical justification of our technique. We provide experimental results on a Verilog RTL implementation of the USB 2.0 functional core, which is a large design with about 1,100 state elements (10331 states). The results demonstrate that the technique provides significant performance benefits over static program slicing using state-of-the-art model checkers.