A symbolic-simulation approach to the timing verification of interacting FSMs
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Operational Semantics for Verilog
APSEC '01 Proceedings of the Eighth Asia-Pacific on Software Engineering Conference
Improved verification of hardware designs through antecedent conditioned slicing
International Journal on Software Tools for Technology Transfer (STTT) - Special Section on Advances in Automated Verification of Critical Systems
Model Checking Verilog Descriptions of Cell Libraries
ACSD '09 Proceedings of the 2009 Ninth International Conference on Application of Concurrency to System Design
Formal Analysis of Non-determinism in Verilog Cell Library Simulation Models
FMICS '09 Proceedings of the 14th International Workshop on Formal Methods for Industrial Critical Systems
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Module paths are often used to specify the delays of cells in a Verilog cell library description, which define the propagation delay for an event from an input to an output. Specifying such paths manually is an error prone task; a forgotten path is interpreted as a zero delay, which can cause further flaws in the subsequent design steps. Moreover, one can specify superfluous module paths, i.e., module paths that can never occur in any practical run of the model and hence, make excessive restrictions on the subsequent design decision. This paper presents a method to check whether the given module paths are reflected in the functional implementation. Complementing this check, we also present a method to derive module paths from a functional description of a cell.