Term rewriting and all that
NuSMV 2: An OpenSource Tool for Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Automatic Generation of Schedulings for Improving the Test Coverage of Systems-on-a-Chip
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Partial order reduction for scalable testing of systemC TLM designs
Proceedings of the 45th annual Design Automation Conference
Model Checking Verilog Descriptions of Cell Libraries
ACSD '09 Proceedings of the 2009 Ninth International Conference on Application of Concurrency to System Design
Test coverage for loose timing annotations
FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology
Checking and deriving module paths in Verilog cell library descriptions
Proceedings of the Conference on Design, Automation and Test in Europe
Symbolic power analysis of cell libraries
FMICS'11 Proceedings of the 16th international conference on Formal methods for industrial critical systems
Formal Analysis of SystemC Designs in Process Algebra
Fundamenta Informaticae
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Cell libraries often contain a simulation model in a system design language, such as Verilog. These languages usually involve non-determinism, which in turn, poses a challenge to their validation. Simulators often resolve such problems by using certain rules to make the specification deterministic. This however is not justified by the behavior of the hardware that is to be modeled. Hence, simulation might not be able to detect certain errors. In this paper we develop a technique to prove whether non-determinism does not affect the behavior of the simulation model, or whether there exists a situation in which the simulation model might produce different results. To make our technique efficient, we show that the global property of equal behavior for all possible evaluations is equivalent to checking only a certain local property.