Formal Analysis of Non-determinism in Verilog Cell Library Simulation Models
FMICS '09 Proceedings of the 14th International Workshop on Formal Methods for Industrial Critical Systems
Checking and deriving module paths in Verilog cell library descriptions
Proceedings of the Conference on Design, Automation and Test in Europe
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We present a formal semantics for a subset of Verilog, commonly used todescribe cell libraries, in terms of transition systems.Such transition systems can serve as input to symbolic model checking,for example equivalence checking with a transistor netlist description. Weimplement our formal semantics as an encoding from the subset of Verilog tothe input language of the SMV model-checker.Experiments show that this approach is able to verify complete cell libraries.