Advances in Petri nets 1986, part II on Petri nets: applications and relationships to other models of concurrency
A framework for object oriented hardware specification, verification, and synthesis
Proceedings of the 38th annual Design Automation Conference
Kronos: A Model-Checking Tool for Real-Time Systems
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Automatic Derivation of Timing Constraints by Failure Analysis
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Dynamic partial-order reduction for model checking software
Proceedings of the 32nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
LusSy: A Toolbox for the Analysis of Systems-on-a-Chip at the Transactional Level
ACSD '05 Proceedings of the Fifth International Conference on Application of Concurrency to System Design
Automatic Generation of Schedulings for Improving the Test Coverage of Systems-on-a-Chip
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Full simulation coverage for SystemC transaction-level models of systems-on-a-chip
Formal Methods in System Design
Formal Analysis of Non-determinism in Verilog Cell Library Simulation Models
FMICS '09 Proceedings of the 14th International Workshop on Formal Methods for Industrial Critical Systems
Verification of an industrial systemC/TLM model using LOTOS and CADP
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
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The design flow of systems-on-a-chip (SoCs) identifies several abstraction levels higher than the Register-Transfer-Level that constitutes the input of the synthesis tools. These levels are called transactional, because systems are described as asynchronous parallel activities communicating by transactions. The most abstract transactional model is purely functional. The following model in the design flow is annotated with some timing information on the duration of the main components, that serves for performance evaluation. The timing annotations are included as special wait instructions, but since the timing information is imprecise, it should not result in additional synchronizations. We would like the functional properties of the system to be independent of the precise timing. In previous work [1], we showed how to adapt dynamic partial order reduction techniques to functional models of SoCs written in SystemC, in order to guarantee that functional properties are scheduler-independent. In this paper, we extend this work to timed systems with bounded delays, in order to guarantee timing-independence. The idea is to generate a set of executions that covers small variations of the timing annotations.