Advances in Petri nets 1986, part II on Petri nets: applications and relationships to other models of concurrency
Defining conditional independence using collapses
Theoretical Computer Science - Selected papers of the International BCS-FACS Workshop on Semantics for Concurrency, Leicester, UK, July 1990
Time, clocks, and the ordering of events in a distributed system
Communications of the ACM
Partial-Order Methods for the Verification of Concurrent Systems: An Approach to the State-Explosion Problem
Automatic Derivation of Timing Constraints by Failure Analysis
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Using Unfoldings to Avoid the State Explosion Problem in the Verification of Asynchronous Circuits
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
WCRE '01 Proceedings of the Eighth Working Conference on Reverse Engineering (WCRE'01)
Dynamic partial-order reduction for model checking software
Proceedings of the 32nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
DART: directed automated random testing
Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
Software Model Checking: The VeriSoft Approach
Formal Methods in System Design
Pinapa: an extraction tool for SystemC descriptions of systems-on-a-chip
Proceedings of the 5th ACM international conference on Embedded software
Formal verification of systemc designs using a petri-net based representation
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Compositional dynamic test generation
Proceedings of the 34th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Automatic Generation of Schedulings for Improving the Test Coverage of Systems-on-a-Chip
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Formal techniques for SystemC verification
Proceedings of the 44th annual Design Automation Conference
Formal verification of SystemC by automatic hardware/software partitioning
MEMOCODE '05 Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design
Partial order reduction for scalable testing of systemC TLM designs
Proceedings of the 45th annual Design Automation Conference
Race analysis for SystemC using model checking
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Test coverage for loose timing annotations
FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology
Distributed dynamic partial order reduction based verification of threaded software
Proceedings of the 14th international SPIN conference on Model checking software
A systemC/TLM semantics in PROMELA and its possible applications
Proceedings of the 14th international SPIN conference on Model checking software
Stateful dynamic partial-order reduction
ICFEM'06 Proceedings of the 8th international conference on Formal Methods and Software Engineering
A conservative approach to systemc parallelization
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part IV
PinaVM: a systemC front-end based on an executable intermediate representation
EMSOFT '10 Proceedings of the tenth ACM international conference on Embedded software
Concurrency-oriented verification and coverage of system-level designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Generation of TLM testbenches using mutation testing
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Completeness-driven development
ICGT'12 Proceedings of the 6th international conference on Graph Transformations
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Transaction-Level Models (TLM) are used for the early validation of embedded software. A TL model is a virtual prototype of the hardware part of a System-on-a-Chip (SoC). When using SystemC for transaction level modeling, the main parallel entities of the hardware platform (processors, DMAs, bus arbiters, etc.) are modeled by asynchronous processes, which are scheduled at simulation time. The specification of this scheduling mechanism is non-deterministic; the set of all possible schedulings of the parallel activities represents the physical parallelism faithfully. Moreover TL models may contain loose timing annotations (intervals for instance), and the set of all possible values of time in these intervals is also meant to represent the hardware behaviors faithfully.However, any simulation engine is built on a deterministic scheduler, and at runtime will use specific values in the time intervals. This means that only a very small subset of all the possible schedulings and timings are exhibited during simulation. Some bugs may be missed if they are due to some behaviors of the hardware that are represented by other schedulings or timings.For a given finite test scenario, the set of valid schedulings and timings of a model is finite, but far too large to be explored fully. We present a solution to cover the set of schedulings and timings efficiently. Our solution is based on dynamic partial order reduction and constraint solving techniques. It gives a complete scheduling and timing set, which guarantees the detection of all local errors and deadlocks for a fixed test scenario.