Test Driven Development: By Example
Test Driven Development: By Example
Coverage Metrics for Temporal Logic Model Checking
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
SystemC: From the Ground Up
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
A Coverage Analysis for Safety Property Lists
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
TTool for DIPLODOCUS: an environment for design space exploration
NOTERE '08 Proceedings of the 8th international conference on New technologies in distributed systems
A temporal language for SystemC
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Full simulation coverage for SystemC transaction-level models of systems-on-a-chip
Formal Methods in System Design
Quality-Driven SystemC Design
Coverage in interpolation-based model checking
Proceedings of the 47th Design Automation Conference
Functional qualification of TLM verification
Proceedings of the Conference on Design, Automation and Test in Europe
Concurrency-oriented verification and coverage of system-level designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ESL Design and Verification: A Prescription for Electronic System Level Methodology
ESL Design and Verification: A Prescription for Electronic System Level Methodology
Analyzing Functional Coverage in Bounded Model Checking
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reusable and correct endogenous model transformations
ICMT'12 Proceedings of the 5th international conference on Theory and Practice of Model Transformations
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Due to the steadily increasing complexity, the design of embedded systems faces serious challenges. To meet these challenges additional abstraction levels have been added to the conventional design flow resulting in Electronic System Level (ESL) design. Besides abstraction, the focus in ESL during the development of a system moves from design to verification, i.e. checking whether or not the system works as intended becomes more and more important. However, at each abstraction level only the validity of certain properties is checked. Completeness, i.e. checking whether or not the entire behavior of the design has been verified, is usually not continuously checked. As a result, bugs may be found very late causing expensive iterations across several abstraction levels. This delays the finalization of the embedded system significantly. In this work, we present the concept of Completeness-Driven Development (CDD). Based on suitable completeness measures, CDD ensures that the next step in the design process can only be entered if completeness at the current abstraction level has been achieved. This leads to an early detection of bugs and accelerates the whole design process. The application of CDD is illustrated by means of an example.