A Framework for Inherent Vacuity
HVC '08 Proceedings of the 4th International Haifa Verification Conference on Hardware and Software: Verification and Testing
Requirements Validation for Hybrid Systems
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Coverage in interpolation-based model checking
Proceedings of the 47th Design Automation Conference
Property analysis and design understanding
Proceedings of the Conference on Design, Automation and Test in Europe
Debugging unrealizable specifications with model-based diagnosis
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
Path predicate abstraction by complete interval property checking
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Improving testbench evaluation using normalized formal properties
VECoS'09 Proceedings of the Third international conference on Verification and Evaluation of Computer and Communication Systems
Completeness-driven development
ICGT'12 Proceedings of the 6th international conference on Graph Transformations
A guiding coverage metric for formal verification
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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We present a coverage analysis that can be used in property-based verification. The analysis helps identifying "forgotten cases"; scenarios where the property list under analysis does not constrain a certain output at a certain point in time. These scenarios can then be manually investigated, possibly leading to new, previously forgotten properties being added. As there often exist cases in which outputs are not supposed to be specified, we also provide means for the specificier to annotate properties in order to control what cases are supposed to be underconstrained. Two main differences with earlier proposed similar analyses exist: The presented analysis is design-independent, and it makes an explicit distinction between intentionally and unintentionally underspecified behavior.