Coverage estimation for symbolic model checking
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Coverage Metrics for Temporal Logic Model Checking
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Automatic Datapath Extraction for Efficient Usage of HDD
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
A Practical Approach to Coverage in Model Checking
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Automatic Datapath Abstraction In Hardware Systems
Proceedings of the 7th International Conference on Computer Aided Verification
Dos and don'ts of CTL state coverage estimation
Proceedings of the 40th annual Design Automation Conference
Assertion-Based Design
Automatic abstraction and verification of verilog models
Proceedings of the 41st annual Design Automation Conference
Scalable Hardware Verification with Symbolic Simulation
Scalable Hardware Verification with Symbolic Simulation
Properties Incompleteness Evaluation by Functional Verification
IEEE Transactions on Computers
SAT-Based Scalable Formal Verification Solutions (Series on Integrated Circuits and Systems)
SAT-Based Scalable Formal Verification Solutions (Series on Integrated Circuits and Systems)
A Coverage Analysis for Safety Property Lists
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
A Quantitative Completeness Analysis for Property-Sets
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
A theory of mutations with applications to vacuity, coverage, and fault tolerance
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Coverage in interpolation-based model checking
Proceedings of the 47th Design Automation Conference
Sanity checks in formal verification
CONCUR'06 Proceedings of the 17th international conference on Concurrency Theory
Analyzing Functional Coverage in Bounded Model Checking
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Unbounded Protocol Compliance Verification Using Interval Property Checking With Invariants
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Considerable effort is made to verify the correct functional behavior of circuits and systems. To guarantee the overall success metric-driven verification flows have been developed. In these flows coverage metrics are omnipresent. Well established coverage metrics for simulation-based verification approaches exist. This is however not the case for formal verification where property checking is a major technique to prove the correctness of the implementation. In this paper we present a guiding coverage metric for this formal verification setting. Our metric reports a single number describing how much of the circuit behavior is uniquely determined by the properties. In addition, the coverage metric guides the verification engineer to achieve completeness by providing helpful information about missing scenarios. This information comes from a new behavior classification algorithm which determines uncovered behavior classes for a signal and allows to compute the coverage of a signal. To measure the complete circuit behavior we devise a coverage metric for a set of signals. The metric is calculated by partitioning the coverage computation into a safe part and an unsafe part where the latter one is weighted accordingly using recursion. This procedure takes into account that in practice properties refer to internal signals which in turn need to be covered them-self. Overall, our metric allows to track the verification progress in property checking and significantly aid the verification engineers in completing the property set.