Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Reasoning about infinite computations
Information and Computation
Formally verifying a microprocessor using a simulation methodology
DAC '94 Proceedings of the 31st annual Design Automation Conference
Efficient generation of counterexamples and witnesses in symbolic model checking
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Software unit test coverage and adequacy
ACM Computing Surveys (CSUR)
What's between simulation and formal verification? (extended abstract)
DAC '98 Proceedings of the 35th annual Design Automation Conference
Coverage estimation for symbolic model checking
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Principles of verifiable RTL design: a functional coding style supporting verification processes in Verilog
Efficient Detection of Vacuity in Temporal Model Checking
Formal Methods in System Design - Special issue on CAV '97
Software reliability methods
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Coverage Metrics for Temporal Logic Model Checking
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
The ForSpec Temporal Logic: A New Temporal Property-Specification Language
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Coverage of Implementations by Simulating Specifications
TCS '02 Proceedings of the IFIP 17th World Computer Congress - TC1 Stream / 2nd IFIP International Conference on Theoretical Computer Science: Foundations of Information Technology in the Era of Networking and Mobile Computing
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
A Practical Approach to Coverage in Model Checking
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Verification Tools for Finite-State Concurrent Systems
A Decade of Concurrency, Reflections and Perspectives, REX School/Symposium
LICS '01 Proceedings of the 16th Annual IEEE Symposium on Logic in Computer Science
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Covering Places and Transitions in Open Nets
BPM '08 Proceedings of the 6th International Conference on Business Process Management
Formal Methods in System Design
Beyond vacuity: towards the strongest passing formula
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
A Framework for Inherent Vacuity
HVC '08 Proceedings of the 4th International Haifa Verification Conference on Hardware and Software: Verification and Testing
Deciding service composition and substitutability using extended operating guidelines
Data & Knowledge Engineering
Finding state solutions to temporal logic queries
IFM'07 Proceedings of the 6th international conference on Integrated formal methods
Proceedings of the 14th international SPIN conference on Model checking software
Coverage in interpolation-based model checking
Proceedings of the 47th Design Automation Conference
A model advisor for NuSMV specifications
Innovations in Systems and Software Engineering
Robust Vacuity for Branching Temporal Logic
ACM Transactions on Computational Logic (TOCL)
Improving the usability of specification languages and methods for annotation-based verification
FMCO'10 Proceedings of the 9th international conference on Formal Methods for Components and Objects
Learning from vacuously satisfiable scenario-based specifications
FASE'12 Proceedings of the 15th international conference on Fundamental Approaches to Software Engineering
Checking sanity of software requirements
SEFM'12 Proceedings of the 10th international conference on Software Engineering and Formal Methods
A guiding coverage metric for formal verification
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Automatic generation of quality specifications
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
Behavioral diagnosis of LTL specifications at operator level
IJCAI'13 Proceedings of the Twenty-Third international joint conference on Artificial Intelligence
Beyond vacuity: towards the strongest passing formula
Formal Methods in System Design
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One of the advantages of temporal-logic model-checking tools is their ability to accompany a negative answer to the correctness query by a counterexample to the satisfaction of the specification in the system. On the other hand, when the answer to the correctness query is positive, most model-checking tools provide no additional information. In the last few years there has been growing awareness to the importance of suspecting the system or the specification of containing an error also in the case model checking succeeds. The main justification of such suspects are possible errors in the modeling of the system or of the specification. The goal of sanity checks is to detect such errors by further automatic reasoning. Two leading sanity checks are vacuity and coverage. In vacuity, the goal is to detect cases where the system satisfies the specification in some unintended trivial way. In coverage, the goal is to increase the exhaustiveness of the specification by detecting components of the system that do not play a role in verification process. For both checks, the challenge is to define vacuity and coverage formally, develop algorithms for detecting vacuous satisfaction and low coverage, and suggest methods for returning to the user helpful information. We survey existing work on vacuity and coverage and argue that, in many aspects, the two checks are essentially the same: both are based on repeating the verification process on some mutant input. In vacuity, mutations are in the specifications, whereas in coverage, mutations are in the system. This observation enables us to adopt work done in the context of vacuity to coverage, and vise versa.