What's between simulation and formal verification? (extended abstract)

  • Authors:
  • David L. Dill

  • Affiliations:
  • Stanford University

  • Venue:
  • DAC '98 Proceedings of the 35th annual Design Automation Conference
  • Year:
  • 1998

Quantified Score

Hi-index 0.00

Visualization

Abstract

This embedded tutorial surveys some possibilities for verification techniques that combine conventional simulation and ideas, techniques, and algorithms from formal verification, to obtain better functional test coverage of large designs.