A guide to simulation (2nd ed.)
A guide to simulation (2nd ed.)
Symbolic model checking: an approach to the state explosion problem
Symbolic model checking: an approach to the state explosion problem
What's between simulation and formal verification? (extended abstract)
DAC '98 Proceedings of the 35th annual Design Automation Conference
ASIC/system hardware verification at Nortel: a view from the trenches
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
A Role for Theorem Proving in Multi-Processor Design
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Model Reductions and a Case Study
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
A Methodology for Large-Scale Hardware Verification
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Applications of Hierarchical Verification in Model Checking
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
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We describe the application of model checking using FormalCheck to an industrial RTL design. It was used as a complement to classical simulation on portions of the chip that involved complex interactions and were difficult to verify by simulation. We also identify certain circuit structures that for a certain type of queries lend themselves to manual model reductions which were not detected by the automatic reduction algorithm. These reductions were instrumental in allowing us to complete the formal verification of the design and to detect two design errors that would have been hard to detect by simulation. We also provide a technique to estimate the length of a random simulation needed to detect a particular design error with a given probability; this length can be used as a measure of its difficulty.