Handbook of theoretical computer science (vol. B)
Online minimization of transition systems (extended abstract)
STOC '92 Proceedings of the twenty-fourth annual ACM symposium on Theory of computing
Symbolic model checking: an approach to the state explosion problem
Symbolic model checking: an approach to the state explosion problem
Testing language containment for &ohgr;-automata using BDDs
Information and Computation
Better verification through symmetry
Formal Methods in System Design - Special issue on symmetry in automatic verification
Exploiting symmetry in temporal logic model checking
Formal Methods in System Design - Special issue on symmetry in automatic verification
A fast state reduction algorithm for incompletely specified finite state machine
DAC '96 Proceedings of the 33rd annual Design Automation Conference
State reduction using reversible rules
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Improved reachability analysis of large finite state machines
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Multiway Decision Graphs for Automated Hardware Verification
Formal Methods in System Design
Bisimulation Minimization in an Automata-Theoretic Verification Framework
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Input Elimination and Abstraction in Model Checking
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Analysis of Discrete Event Coordination
Stepwise Refinement of Distributed Systems, Models, Formalisms, Correctness, REX Workshop
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Model checking for a first-order temporal logic using multiway decision graphs
Model checking for a first-order temporal logic using multiway decision graphs
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In this paper, we present a model reduction algorithm for property checking. For the property to be verified, we first construct a property dependency graph which represents the function dependency of the property on variables. Beginning from the set of state variables appearing in the property, we search through the property dependency graph and add a noncorrelated set of state variables to the current set of state variables to construct a more detailed model at each reduction iteration step. The final reduced model is the one which is constructed by using all state variables that can be reached in the graph. The final reduced model preserves the property strongly, while the intermediate reduced models preserve the property weakly. Our reduction algorithm is completely automatic. Since there is no preimage operation in MDG (Multiway Decision Graph) model checker due to the presence of abstract state variables, all backward reduction algorithms cannot be used in MDG. Our method is suitable for MDG and has been implemented in this tool, however, it can be used in other tools as well. We then discuss a quite common circuit structure which appears in telecommunication and data processing circuits. We use three verification tools MDG, FormalCheck and SMV to verify this circuit. The experimental results show that our reduction algorithm is more efficient on these typical structures.