Model checking and modular verification
ACM Transactions on Programming Languages and Systems (TOPLAS)
Model checking, abstraction, and compositional verification
Model checking, abstraction, and compositional verification
Efficient generation of counterexamples and witnesses in symbolic model checking
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
DAC '97 Proceedings of the 34th annual Design Automation Conference
Another Look at LTL Model Checking
Formal Methods in System Design
Early Quantification and Partitioned Transition Relations
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
A Compositional Rule for Hardware Design Refinement
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Model Reductions and a Case Study
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Applications of Hierarchical Verification in Model Checking
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Model Checking the IBM Gigahertz Processor: An Abstraction Algorithm for High-Performance Netlists
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Fifteen Years of Formal Property Verification in Intel
25 Years of Model Checking
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
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Symbolic model checking, while gaining success in the industry as a valuable tool for finding hardware design bugs, is still severely limited with respect to the size of the verifiable designs. This limitation is due to the nonlinear memory consumption of the data structure (namely, BDD and its variants) used to represent the model and the explored states. Input elimination is a known method that reduces the size of the model by existential quantification of the inputs. In this paper, we improve this technique in several dimensions: we present a novel re-encoding of the model that results in a much large set of quantifiable inputs, we introduce a new greedy algorithm for early quantification of the inputs during the transition relation build, and we suggest a new algorithm to reconstruct the input values in an error trace. Model abstraction is a semiautomatic method that requires the user to provide an abstraction mapping, and can dramatically reduce the size of models with large data-path. We show that data abstraction can be reduced to input elimination using few simple manipulations of the hardware netlist description. Model abstraction is a wellknown technique and our contribution is a novel technique that generates the minimal transition relation with respect to a given abstraction mapping.