Proceedings of the Fourth Annual Symposium on Logic in computer science
Linking BDD-based symbolic evaluation to interactive theorem-proving
DAC '93 Proceedings of the 30th international Design Automation Conference
Model checking and abstraction
ACM Transactions on Programming Languages and Systems (TOPLAS)
Formal verification of FIRE: a case study
DAC '97 Proceedings of the 34th annual Design Automation Conference
Formal verification using parametric representations of Boolean constraints
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
Formal verification of iterative algorithms in microprocessors
Proceedings of the 37th Annual Design Automation Conference
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Input Elimination and Abstraction in Model Checking
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
The Formal Design of 1M-gate ASICs
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
A Hybrid Approach to Verifying Liveness in a Symmetric Multi-Processor
TPHOLs '97 Proceedings of the 10th International Conference on Theorem Proving in Higher Order Logics
Lifted-FL: A Pragmatic Implementation of Combined Model Checking and Theorem Proving
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Automatic Datapath Extraction for Efficient Usage of HDD
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Verification of Floating-Point Adders
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
WIFT '95 Proceedings of the 1st Workshop on Industrial-Strength Formal Specification Techniques
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The LTL model checker that we use provides sound decomposition mechanisms within a purely model checking environment.We have exploited these mechanisms to successfully verify a wide spectrum of large and complex circuits. This paper describes a variety of the decomposition techniques that we have used as part of a large industrial formal verification effort on the Intel Pentium® 4 (Willamette) processor.