Formal Methods Applied to a Floating-Point Number System
IEEE Transactions on Software Engineering
Programming: the derivation of algorithms
Programming: the derivation of algorithms
Trace algebra for automatic verification of real-time concurrent systems
Trace algebra for automatic verification of real-time concurrent systems
Model checking and abstraction
ACM Transactions on Programming Languages and Systems (TOPLAS)
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
Bit-level analysis of an SRT divider circuit
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Combining theorem proving and trajectory evaluation in an industrial environment
DAC '98 Proceedings of the 35th annual Design Automation Conference
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
A Mechanically Checked Proof of the AMD5K86TM Floating-Point Division Program
IEEE Transactions on Computers
Formal verification using parametric representations of Boolean constraints
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
The Science of Programming
Non-Restoring Integer Square Root: A Case Study in Design by Principled Optimization
TPCD '94 Proceedings of the Second International Conference on Theorem Provers in Circuit Design - Theory, Practice and Experience
Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Verifying the SRT Division Algorithm Using Theorem Proving Techniques
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Symbolic Trajectory Evaluation
Formal Hardware Verification - Methods and Systems in Comparison
VOSS - A Formal Hardware Verification System User''s Guide
VOSS - A Formal Hardware Verification System User''s Guide
Solving the generalized mask constraint for test generation of binary floating point add operation
Theoretical Computer Science - Real numbers and computers
Mechanical Verification of a Square Root Algorithm Using Taylor's Theorem
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Divider Circuit Verification with Model Checking and Theorem Proving
TPHOLs '00 Proceedings of the 13th International Conference on Theorem Proving in Higher Order Logics
Applications of Hierarchical Verification in Model Checking
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Formally Linking MDG and HOL Based on a Verified MDG System
IFM '02 Proceedings of the Third International Conference on Integrated Formal Methods
Verifying a gigabit ethernet switch using SMV
Proceedings of the 41st annual Design Automation Conference
Formal Verification of the VAMP Floating Point Unit
Formal Methods in System Design
A reflective functional language for hardware design and theorem proving
Journal of Functional Programming
Providing a formal linkage between MDG and HOL
Formal Methods in System Design
An abstract reachability approach by combining HOL induction and multiway decision graphs
Journal of Computer Science and Technology
Challenges for formal verification in industrial setting
FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology
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Contemporary microprocessors implement many iterative algorithms. For example, the front-end of a microprocessor repeatedly fetches and decodes instructions while updating internal state such as the program counter; floating-point circuits perform divide and square root computations iteratively. Iterative algorithms often have complex implementations because of performance optimizations like result speculation, re-timing and circuit redundancies. Verifying these iterative circuits against high-level specifications requires two steps: reasoning about the algorithm itself and verifying the implementation against the algorithm. In this paper we discuss the verification of four iterative circuits from Intel microprocessor designs. These verifications were performed using Forte, a custom-built verification system; we discuss the Forte features necessary for our approach. Finally, we discuss how we maintained these proofs in the face of evolving design implementations.