Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Toward compiler implementation correctness proofs
ACM Transactions on Programming Languages and Systems (TOPLAS)
ML for the working programmer
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Introduction to Maple
Introduction to HOL: a theorem proving environment for higher order logic
Introduction to HOL: a theorem proving environment for higher order logic
Linking BDD-based symbolic evaluation to interactive theorem-proving
DAC '93 Proceedings of the 30th international Design Automation Conference
Higher order logic and hardware verification
Higher order logic and hardware verification
Formal verification of iterative algorithms in microprocessors
Proceedings of the 37th Annual Design Automation Conference
A Skeptic’s Approach to Combining HOL and Maple
Journal of Automated Reasoning
A Machine-Checked Implementation of Buchberger's Algorithm
Journal of Automated Reasoning
Multiway Decision Graphs for Automated Hardware Verification
Formal Methods in System Design
Detecting Multiple Classes of User Errors
EHCI '01 Proceedings of the 8th IFIP International Conference on Engineering for Human-Computer Interaction
Experience with Embedding Hardware Description Languages in HOL
Proceedings of the IFIP TC10/WG 10.2 International Conference on Theorem Provers in Circuit Design: Theory, Practice and Experience
Formal Verification of the Island Tunnel Controller Using Multiway Decision Graphs
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Three Approaches to Hardware Verification: HOL, MDG and VIS Compared
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Formal Verification of a Partial-Order Reduction Technique for Model Checking
TACAs '96 Proceedings of the Second International Workshop on Tools and Algorithms for Construction and Analysis of Systems
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
Verified Bytecode Model Checkers
TPHOLs '02 Proceedings of the 15th International Conference on Theorem Proving in Higher Order Logics
Combinations of Model Checking and Theorem Proving
FroCoS '00 Proceedings of the Third International Workshop on Frontiers of Combining Systems
An Integration of Model Checking with Automated Proof Checking
Proceedings of the 7th International Conference on Computer Aided Verification
Symbolic Trajectory Evaluation
Formal Hardware Verification - Methods and Systems in Comparison
TPHOLs 2000: Supplemental Proceedings
TPHOLs 2000: Supplemental Proceedings
An abstract reachability approach by combining HOL induction and multiway decision graphs
Journal of Computer Science and Technology
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We describe an approach for formally verifying the linkage between a symbolic state enumeration system and a theorem proving system. This involves the following three stages of proof. Firstly we prove theorems about the correctness of the translation part of the symbolic state system. It interfaces between low level decision diagrams and high level description languages. We ensure that the semantics of a program is preserved in those of its translated form. Secondly we prove linkage theorems: theorems that justify introducing a result from a state enumeration system into a proof system. Finally we combine the translator correctness and linkage theorems. The resulting new linkage theorems convert results to a high level language from the low level decision diagrams that the result was actually proved about in the state enumeration system. They justify importing low-level external verification results into a theorem prover. We use a linkage between the HOL system and a simplified version of the MDG system to illustrate the ideas and consider a small example that integrates two applications from MDG and HOL to illustrate the linkage theorems.