Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Programming in Prolog
Introduction to HOL: a theorem proving environment for higher order logic
Introduction to HOL: a theorem proving environment for higher order logic
Combining theorem proving and trajectory evaluation in an industrial environment
DAC '98 Proceedings of the 35th annual Design Automation Conference
Formal hardware verification by integrating HOL and MDG
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Formal verification of iterative algorithms in microprocessors
Proceedings of the 37th Annual Design Automation Conference
From LCF to HOL: a short history
Proof, language, and interaction
Introduction to Formal Hardware Verification: Methods and Tools for Designing Correct Circuits and Systems
Symbolic Model Checking
Computer-Aided Reasoning: An Approach
Computer-Aided Reasoning: An Approach
Multiway Decision Graphs for Automated Hardware Verification
Formal Methods in System Design
Formal Verification of the Island Tunnel Controller Using Multiway Decision Graphs
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Do You Trust Your Model Checker?
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
The HOL-Voss System: Model-Checking inside a General-Purpose Theorem-Prover
HUG '93 Proceedings of the 6th International Workshop on Higher Order Logic Theorem Proving and its Applications
An Integration of Model Checking with Automated Proof Checking
Proceedings of the 7th International Conference on Computer Aided Verification
On the non-termination of MDG-based abstract state enumeration
Theoretical Computer Science
An Introduction to Requirements Capture Using PVS: Specification of a Simple Autopilot
An Introduction to Requirements Capture Using PVS: Specification of a Simple Autopilot
VOSS - A Formal Hardware Verification System User''s Guide
VOSS - A Formal Hardware Verification System User''s Guide
Hybrid verification integrating HOL theorem proving with MDG model checking
Microelectronics Journal
Providing a formal linkage between MDG and HOL
Formal Methods in System Design
Reachability analysis using multiway decision graphs in the HOL theorem prover
Proceedings of the 2008 ACM symposium on Applied computing
Verification of BDD normalization
TPHOLs'05 Proceedings of the 18th international conference on Theorem Proving in Higher Order Logics
MDG-SAT: an automated methodology for efficient safety checking
International Journal of Critical Computer-Based Systems
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In this paper, we provide a necessary infrastructure to define an abstract state exploration in the HOL theorem prover. Our infrastructure is based on a deep embedding of the Multiway Decision Graphs (MDGs) theory in HOL. MDGs generalize Reduced Ordered Binary Decision Diagrams (ROBDDs) to represent and manipulate a subset of first-order logic formulae. The MDGs embedding is based on the logical formulation of an MDG as Directed Formulae (DF). Then, the MDGs operations are defined and the correctness proof of each operation is provided. The MDG reachability algorithm is then defined as a conversion that uses our MDG theory within HOL. Finally, a set of experimentations over benchmark circuits has been conducted to ensure the applicability and to measure the performance of our approach.