Hybrid verification integrating HOL theorem proving with MDG model checking

Authors:
Rabeb Mizouni;Sofiène Tahar;Paul Curzon
Affiliations:
Department of Electrical and Computer Engineering, Concordia University, Montreal, Que., Canada H3G 1M8;Department of Electrical and Computer Engineering, Concordia University, Montreal, Que., Canada H3G 1M8;Department of Computer Science, Queen Mary University of London, Mile End, London E1 4NS, UK
Venue:
Microelectronics Journal
Year:
2006

Citing 9
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Abstract

In this paper, we describe a hybrid tool for hardware formal verification that links the HOL (higher-order logic) theorem prover and the MDG (multiway decision graphs) model checker. Our tool supports abstract datatypes and uninterpreted function symbols available in MDG, allowing the verification of high-level specifications. The hybrid tool, HOL-MDG, is based on an embedding in HOL of the grammar of the hardware modeling language, MDG-HDL, as well as an embedding of the first-order temporal logic L"m"d"g used to express properties for the MDG model checker. Verification with the hybrid tool is faster and more tractable than using either tools separately. We hence obtain the advantages of both verification paradigms.