Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs

Formal hardware verification by integrating HOL and MDG

GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI

Term ordering problem on MDG

Proceedings of the 12th ACM Great Lakes symposium on VLSI

Model Reductions and a Case Study

FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design

Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs

FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design

Formal Verification of a SONET Telecom System Block

ICFEM '02 Proceedings of the 4th International Conference on Formal Engineering Methods: Formal Methods and Software Engineering

Language emptiness checking using MDGs

Proceedings of the 13th ACM Great Lakes symposium on VLSI

Hybrid verification integrating HOL theorem proving with MDG model checking

Microelectronics Journal

Formal verification of ASMs using MDGs

Journal of Systems Architecture: the EUROMICRO Journal

Interfacing ASM with the MDG tool

ASM'03 Proceedings of the abstract state machines 10th international conference on Advances in theory and practice

Static slicing-based pre-reduction technique for MDG model-checker

IIT'09 Proceedings of the 6th international conference on Innovations in information technology

Abstract property language for MDG model checking methodology

International Journal of Computer Applications in Technology

LTL model-checking for malware detection

TACAS'13 Proceedings of the 19th international conference on Tools and Algorithms for the Construction and Analysis of Systems