Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Verification of synchronous sequential machines based on symbolic execution
Proceedings of the international workshop on Automatic verification methods for finite state systems
Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Introduction to HOL: a theorem proving environment for higher order logic
Introduction to HOL: a theorem proving environment for higher order logic
On-the-Fly Model Checking of RCTL Formulas
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
FoCs: Automatic Generation of Simulation Checkers from Formal Specifications
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Verification with Abstract State Machines Using MDGs
Formal Hardware Verification - Methods and Systems in Comparison
PVS: A Prototype Verification System
CADE-11 Proceedings of the 11th International Conference on Automated Deduction: Automated Deduction
Model checking for a first-order temporal logic using multiway decision graphs
Model checking for a first-order temporal logic using multiway decision graphs
On the Design and Verification Methodology of the Look-Aside Interface
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Incorporating Ef.cient Assertion Checkers into Hardware Emulation
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Proven correct monitors from PSL specifications
Proceedings of the conference on Design, automation and test in Europe: Proceedings
From PSL to LTL: a formal validation in HOL
TPHOLs'05 Proceedings of the 18th international conference on Theorem Proving in Higher Order Logics
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In this paper, we propose a new specification language called Abstract Property Language (APL) suitable for Multiway Decision Graph (MDG) Model Checking (MC) that replaces LMDG language and introduces new operators obtained from Property Specification Language (PSL). The purpose is to improve expressiveness and to enhance MC verification technique in MDG. Though, the PSL language was modified to model system properties at the same level of abstraction. We provide formal definition in BNF grammar format and formal semantics. APL is associated with a front-end translator that accepts APL specifications and builds verification-ready models to be handled by MDG tool.