Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Modalities for model checking: branching time logic strikes back
Science of Computer Programming
A hierarchy of temporal properties (invited paper, 1989)
PODC '90 Proceedings of the ninth annual ACM symposium on Principles of distributed computing
Handbook of theoretical computer science (vol. B)
Formal specification in VHDL for hardware verification
Proceedings of the conference on Design, automation and test in Europe
On the temporal analysis of fairness
POPL '80 Proceedings of the 7th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
IEEE Standards Intepretations: IEEE Std 1076-1987, IEEE Standard VHDL Language Reference Manual
IEEE Standards Intepretations: IEEE Std 1076-1987, IEEE Standard VHDL Language Reference Manual
Improving Automata Generation for Linear Temporal Logic by Considering the Automaton Hierarchy
LPAR '01 Proceedings of the Artificial Intelligence on Logic for Programming
Simple on-the-fly automatic verification of linear temporal logic
Proceedings of the Fifteenth IFIP WG6.1 International Symposium on Protocol Specification, Testing and Verification XV
The ForSpec Temporal Logic: A New Temporal Property-Specification Language
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
A HOL Conversion for Translating Linear Time Temporal Logic to omega-Automata
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
Improved Automata Generation for Linear Temporal Logic
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Efficient Büchi Automata from LTL Formulae
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Fast LTL to Büchi Automata Translation
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Verification of Reactive Systems: Formal Methods and Algorithms
Verification of Reactive Systems: Formal Methods and Algorithms
Bounded model checking of infinite state systems
Formal Methods in System Design
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
Temporal logic can be more expressive
SFCS '81 Proceedings of the 22nd Annual Symposium on Foundations of Computer Science
Reasoning about infinite computation paths
SFCS '83 Proceedings of the 24th Annual Symposium on Foundations of Computer Science
Resets vs. aborts in linear temporal logic
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Proven correct monitors from PSL specifications
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Model checking PSL using HOL and SMV
HVC'06 Proceedings of the 2nd international Haifa verification conference on Hardware and software, verification and testing
SALT—structured assertion language for temporal logic
ICFEM'06 Proceedings of the 8th international conference on Formal Methods and Software Engineering
Abstract property language for MDG model checking methodology
International Journal of Computer Applications in Technology
| Hi-index | 0.00 |
Using the HOL theorem prover, we proved the correctness of a translation from a subset of Accellera's property specification language PSL to linear temporal logic LTL. Moreover, we extended the temporal logic hierarchy of LTL that distinguishes between safety, liveness, and more difficult properties to PSL . The combination of the translation from PSL to LTL with already available translations from LTL to corresponding classes of ω-automata yields an efficient translation from PSL to ω-automata. In particular, this translation generates liveness or safety automata for corresponding PSL fragments, which is important for several applications like bounded model checking.