“Sometimes” and “not never” revisited: on branching versus linear time temporal logic
Journal of the ACM (JACM) - The MIT Press scientific computation series
A hierarchy of temporal properties (invited paper, 1989)
PODC '90 Proceedings of the ninth annual ACM symposium on Principles of distributed computing
Handbook of theoretical computer science (vol. B)
Handbook of theoretical computer science (vol. B)
Introduction to HOL: a theorem proving environment for higher order logic
Introduction to HOL: a theorem proving environment for higher order logic
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
A linear-time model-checking algorithm for the alternation-free modal mu-calculus
Formal Methods in System Design - Special issue on computer-aided verification: special methods II
Reasoning about infinite computations
Information and Computation
CTL and equivalent sublanguages of CTL
CHDL'97 Proceedings of the IFIP TC10 WG10.5 international conference on Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems: specification, modelling, verification and synthesis of microelectronic systems
Modalities for model checking (extended abstract): branching time strikes back
POPL '85 Proceedings of the 12th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Checking that finite state concurrent programs satisfy their linear specification
POPL '85 Proceedings of the 12th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Symbolic Model Checking
Constructing automata from temporal logic formulas: a tutorial
Lectures on formal methods and performance analysis
Simple on-the-fly automatic verification of linear temporal logic
Proceedings of the Fifteenth IFIP WG6.1 International Symposium on Protocol Specification, Testing and Verification XV
Studies of the Single Pulser in Various Reasoning Systems
TPCD '94 Proceedings of the Second International Conference on Theorem Provers in Circuit Design - Theory, Practice and Experience
Model Checking on Product Structures
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
A Comparative Study of Symbolic Algorithms for the Computation of Fair Cycles
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
An Algorithm for Strongly Connected Component Analysis in n log n Symbolic Steps
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Branching vs. Linear Time: Final Showdown
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Efficient CTL* model checking for analysis of rainbow designs
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
Efficient Büchi Automata from LTL Formulae
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Another Look at LTL Model Checking
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Algorithmic Verification of Linear Temporal Logic Specifications
ICALP '98 Proceedings of the 25th International Colloquium on Automata, Languages and Programming
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
SMT-based optimization for synchronous programs
Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems
A multi-encoding approach for LTL symbolic satisfiability checking
FM'11 Proceedings of the 17th international conference on Formal methods
A new algorithm for strategy synthesis in LTL games
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Shortest counterexamples for symbolic model checking of LTL with past
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
From PSL to LTL: a formal validation in HOL
TPHOLs'05 Proceedings of the 18th international conference on Theorem Proving in Higher Order Logics
An asymptotically correct finite path semantics for LTL
LPAR'12 Proceedings of the 18th international conference on Logic for Programming, Artificial Intelligence, and Reasoning
Deterministic compilation of temporal safety properties in explicit state model checking
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
Passive code in synchronous programs
ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
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We present newalgorithms to translate linear time temporal logic (LTL) formulas with past operators to equivalent ω-automata. The resulting automata are given in a symbolic representation that directly supports symbolic model checking. Furthermore, this has the advantage that the translations run in linear time wrt. the length of the input formula. To increase the efficiency of the model checking, our translations avoid as far as possible the introduction of computationally expensive fairness constraints, or at least replace them by simpler reachability constraints. Using the well-known automaton hierarchy, we show that our improvements are complete. Finally, we show how large parts of the formulas can be translated to the simpler logic CTL, which accelerates the LTL model checking by orders of magnitude which is shown by experimental results.