Parallel program design: a foundation
Parallel program design: a foundation
The ESTEREL synchronous programming language: design, semantics, implementation
Science of Computer Programming
I/O- and CPU-optimal recognition of strongly connected components2
Information Processing Letters
CTL and ECTL as fragments of the modal &mgr;-calculus
Theoretical Computer Science - Selected papers of the 17th Colloquium on Trees in Algebra and Programming (CAAP '92) and of the European Symposium on Programming (ESOP), Rennes, France, Feb. 1992
Data flow analysis is model checking of abstract interpretations
POPL '98 Proceedings of the 25th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Characterizations of Reducible Flow Graphs
Journal of the ACM (JACM)
Communications of the ACM
Guarded commands, nondeterminacy and formal derivation of programs
Communications of the ACM
On model checking for the &mgr;-calculus and its fragments
Theoretical Computer Science
Analysis of a simple algorithm for global data flow problems
POPL '73 Proceedings of the 1st annual ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Synchronous Programming of Reactive Systems
Synchronous Programming of Reactive Systems
Improving Automata Generation for Linear Temporal Logic by Considering the Automaton Hierarchy
LPAR '01 Proceedings of the Artificial Intelligence on Logic for Programming
Data Flow Analysis as Model Checking
TACS '91 Proceedings of the International Conference on Theoretical Aspects of Computer Software
An Algorithm for Strongly Connected Component Analysis in n log n Symbolic Steps
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Proving the Equivalence of Microstep and Macrostep Semantics
TPHOLs '02 Proceedings of the 15th International Conference on Theorem Proving in Higher Order Logics
A Verified Hardware Synthesis of Esterel Programs
DIPES '00 Proceedings of the IFIP WG10.3/WG10.4/WG10.5 International Workshop on Distributed and Parallel Embedded Systems: Architecture and Design of Distributed Embedded Systems
TAXYS: A Tool for the Development and Verification of Real-Time Embedded Systems
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Faster Model Checking for the Modal Mu-Calculus
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
On Model-Checking for Fragments of µ-Calculus
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
The Murphi Verification System
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Embedding Imperative Synchronous Languages in Interactive Theorem Provers
ACSD '01 Proceedings of the Second International Conference on Application of Concurrency to System Design
Proceedings of a symposium on Compiler optimization
Optimizations for Faster Execution of Esterel Programs
MEMOCODE '03 Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
Verification of Reactive Systems: Formal Methods and Algorithms
Verification of Reactive Systems: Formal Methods and Algorithms
Abstraction of assembler programs for symbolic worst case execution time analysis
Proceedings of the 41st annual Design Automation Conference
Generating fast code from concurrent program dependence graphs
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Exact High Level WCET Analysis of Synchronous Programs by Symbolic State Space Exploration
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Causality analysis of synchronous programs with delayed actions
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Compiling Esterel
Separate compilation for synchronous programs
Proceedings of th 12th International Workshop on Software and Compilers for Embedded Systems
Context-sensitive timing analysis of Esterel programs
Proceedings of the 46th Annual Design Automation Conference
A Verified Compiler for Synchronous Programs with Local Declarations
Electronic Notes in Theoretical Computer Science (ENTCS)
Compiling Esterel into Static Discrete-Event Code
Electronic Notes in Theoretical Computer Science (ENTCS)
Static data-flow analysis of synchronous programs
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Instantaneous termination in pure Esterel
SAS'03 Proceedings of the 10th international conference on Static analysis
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
Timing analysis of esterel programs on general-purpose multiprocessors
Proceedings of the 47th Design Automation Conference
Data-Flow Analysis of Extended Finite State Machines
ACSD '11 Proceedings of the 2011 Eleventh International Conference on Application of Concurrency to System Design
Implicit enumeration of strongly connected components and an application to formal verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Esterel compiler for large control-dominated systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
XEEMU: an improved xscale power simulator
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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The synchronous model of computation requires that in every step, inputs are read and outputs are synchronously computed as the reaction of the program. In addition, all internal variables are updated in parallel even though not all of these values might be required for the current and the future reaction steps. To avoid unnecessary computations, we present a compile-time optimization procedure that computes for every variable a condition that determines whether its value is required for current or future computations. In this sense, our optimizations allow us to identify passive code that can be disabled to avoid unnecessary computations and therefore to reduce the reaction time of programs or their energy consumption.