Parallel program design: a foundation
Parallel program design: a foundation
The ESTEREL synchronous programming language: design, semantics, implementation
Science of Computer Programming
GC: the data-flow graph format of synchronous programming
IR '95 Papers from the 1995 ACM SIGPLAN workshop on Intermediate representations
Synchronous languages for hardware and software reactive systems
CHDL'97 Proceedings of the IFIP TC10 WG10.5 international conference on Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems: specification, modelling, verification and synthesis of microelectronic systems
Compiling Esterel into sequential code
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
ECL: a specification environment for system-level design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proof, language, and interaction
A new method for compiling schizophrenic synchronous programs
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Synchronous Programming of Reactive Systems
Synchronous Programming of Reactive Systems
Proving the Equivalence of Microstep and Macrostep Semantics
TPHOLs '02 Proceedings of the 15th International Conference on Theorem Proving in Higher Order Logics
A Verified Hardware Synthesis of Esterel Programs
DIPES '00 Proceedings of the IFIP WG10.3/WG10.4/WG10.5 International Workshop on Distributed and Parallel Embedded Systems: Architecture and Design of Distributed Embedded Systems
The Murphi Verification System
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Implementing Reactive Programs on Circuits: A Hardware Implementation of LUSTRE
Proceedings of the Real-Time: Theory in Practice, REX Workshop
Embedding Imperative Synchronous Languages in Interactive Theorem Provers
ACSD '01 Proceedings of the Second International Conference on Application of Concurrency to System Design
Optimizations for Faster Execution of Esterel Programs
MEMOCODE '03 Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
Formal analysis of synchronous circuits
Formal analysis of synchronous circuits
Causality analysis of synchronous programs with delayed actions
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
ACSD '05 Proceedings of the Fifth International Conference on Application of Concurrency to System Design
A causality interface for deadlock analysis in dataflow
EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
A Verified Compiler for Synchronous Programs with Local Declarations
Electronic Notes in Theoretical Computer Science (ENTCS)
Separate compilation for synchronous modules
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
An Esterel compiler for large control-dominated systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Static data-flow analysis of synchronous programs
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Translating concurrent action oriented specifications to synchronous guarded actions
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Multithreaded code from synchronous programs: extracting independent threads for OpenMP
Proceedings of the Conference on Design, Automation and Test in Europe
SMT-based optimization for synchronous programs
Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems
Detection of harmful schizophrenic statements in esterel
ACM Transactions on Embedded Computing Systems (TECS)
Passive code in synchronous programs
ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
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Esterel and other imperative synchronous languages offer a rich set of statements, which can be used to conveniently describe complex control behaviors in a concise, but yet precise way. In particular, the ability to arbitrarily nest all kinds of statements including loops, local declarations, sequential and parallel control, as well as several kinds of preemption statements leads to a powerful programming language. However, this orthogonal design imposes difficult problems for the modular or separate compilation, which has to deal with special problems like the instantaneous reincarnation of locally declared variables. This paper presents a compilation procedure allowing to separately compile modules of a synchronous language. Our approach is based on two new achievements: First, we derive the information that is required for a linker to combine already compiled modules. This information is stored in a file written in an intermediate format, which is the target of our compilation procedure and the source of the linker. Second, we describe a compilation procedure for a typical imperative synchronous language to generate this intermediate format. We have implemented the approach in the upcoming version 2.0 of our Averest system.