Supervisory control of a class of discrete event processes
SIAM Journal on Control and Optimization
Parallel program design: a foundation
Parallel program design: a foundation
POLLUX: a LUSTRE based hardware design environment
Proceedings of the international workshop on Algorithms and parallel VLSI architectures II
Synchronous languages for hardware and software reactive systems
CHDL'97 Proceedings of the IFIP TC10 WG10.5 international conference on Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems: specification, modelling, verification and synthesis of microelectronic systems
Guarded commands, nondeterminacy and formal derivation of programs
Communications of the ACM
Synchronous Programming of Reactive Systems
Synchronous Programming of Reactive Systems
Proving the Equivalence of Microstep and Macrostep Semantics
TPHOLs '02 Proceedings of the 15th International Conference on Theorem Proving in Higher Order Logics
The Murphi Verification System
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Embedding Imperative Synchronous Languages in Interactive Theorem Provers
ACSD '01 Proceedings of the Second International Conference on Application of Concurrency to System Design
Formal analysis of synchronous circuits
Formal analysis of synchronous circuits
Modular scheduling of guarded atomic actions
Proceedings of the 41st annual Design Automation Conference
Causality analysis of synchronous programs with delayed actions
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Combining supervisor synthesis and model checking
ACM Transactions on Embedded Computing Systems (TECS)
ACSD '05 Proceedings of the Fifth International Conference on Application of Concurrency to System Design
Scheduling as Rule Composition
MEMOCODE '07 Proceedings of the 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign
Spin model checker, the: primer and reference manual
Spin model checker, the: primer and reference manual
Separate compilation for synchronous programs
Proceedings of th 12th International Workshop on Software and Compilers for Embedded Systems
A Verified Compiler for Synchronous Programs with Local Declarations
Electronic Notes in Theoretical Computer Science (ENTCS)
Operation-centric hardware description and synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Concurrent Action-Oriented Specifications (CAOS) model the be- havior of a synchronous hardware circuit as asynchronous guarded actions at an abstraction level higher than the Register Transfer Level (RTL). Previous approaches always considered the compilation of CAOS, which includes a transformation of the under-lying model of computation and the scheduling of guarded actions per clock cycle, as a tightly integrated step. In this paper, we present a new compilation procedure, which separates these two tasks and translates CAOS models to synchronous guarded actions with an explicit interface to a scheduler. This separation of con- cerns has many advantages, including better analyses and integration of custom schedulers. Our method also generates assertions that each scheduler must obey that can be fulfilled by algorithms for scheduler synthesis like those developed in supervisory control. We present our translation procedure in detail and illustrate it by various examples. We also show that our method simplifies for- mal verification of hardware synthesized from CAOS specifications over previously known formal verification approaches.