Bounded model checking of infinite state systems
Formal Methods in System Design
Formal Reasoning About Causality Analysis
TPHOLs '08 Proceedings of the 21st International Conference on Theorem Proving in Higher Order Logics
Separate compilation for synchronous programs
Proceedings of th 12th International Workshop on Software and Compilers for Embedded Systems
A Verified Compiler for Synchronous Programs with Local Declarations
Electronic Notes in Theoretical Computer Science (ENTCS)
Static data-flow analysis of synchronous programs
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Translating concurrent action oriented specifications to synchronous guarded actions
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Constructive semantics for instantaneous reactions
Theoretical Computer Science
Approximate reachability for dead code elimination in esterel
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
A hoare calculus for the verification of synchronous languages
PLPV '12 Proceedings of the sixth workshop on Programming languages meets program verification
Dependable polygon-processing algorithms for safety-critical embedded systems
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
Constructive Boolean circuits and the exactness of timed ternary simulation
Formal Methods in System Design
Hi-index | 0.00 |
Message sequence charts (MSC) are a graphical notation standardized by the ITU and used for the description of communication scenarios between asynchronous processes. This talk concerns the formal analysis of MSC-based specifications in relation with ...