Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
A fast mutual exclusion algorithm
ACM Transactions on Computer Systems (TOCS)
Calculating the maximum, execution time of real-time programs
Real-Time Systems
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Verus: a tool for quantitative analysis of finite-state real-time systems
LCTES '95 Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems
The STATEMATE semantics of statecharts
ACM Transactions on Software Engineering and Methodology (TOSEM)
Proof, language, and interaction
Synchronous Programming of Reactive Systems
Synchronous Programming of Reactive Systems
Deriving Annotations for Tight Calculation of Execution Time
Euro-Par '97 Proceedings of the Third International Euro-Par Conference on Parallel Processing
Automatic Accurate Time-Bound Analysis for High-Level Languages
LCTES '98 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques
LCTES '98 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
A Verified Hardware Synthesis of Esterel Programs
DIPES '00 Proceedings of the IFIP WG10.3/WG10.4/WG10.5 International Workshop on Distributed and Parallel Embedded Systems: Architecture and Design of Distributed Embedded Systems
Selective Quantitative Analysis and Interval Model Checking: Verifying Different Facets of a System
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Embedding Imperative Synchronous Languages in Interactive Theorem Provers
ACSD '01 Proceedings of the Second International Conference on Application of Concurrency to System Design
A New Approach to the Specification and Verification of Real-Time Systems
ECRTS '01 Proceedings of the 13th Euromicro Conference on Real-Time Systems
Extending Synchronous Languages for Generating Abstract Real-Time Models
Proceedings of the conference on Design, automation and test in Europe
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Abstraction of assembler programs for symbolic worst case execution time analysis
Proceedings of the 41st annual Design Automation Conference
Causality analysis of synchronous programs with delayed actions
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
An Esterel processor with full preemption support and its worst case reaction time analysis
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Worst Case Reaction Time Analysis of Concurrent Reactive Programs
Electronic Notes in Theoretical Computer Science (ENTCS)
Abstract Interpretation with Applications to Timing Validation
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Compilation and worst-case reaction time analysis for multithreaded Esterel processing
EURASIP Journal on Embedded Systems - Model-driven high-level programming of embedded systems: selected papers from SLA++P'07 and SLA++P'08
Symbolic state traversal for WCET analysis
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
WCRT algebra and interfaces for Esterel-style synchronous processing
Proceedings of the Conference on Design, Automation and Test in Europe
Passive code in synchronous programs
ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
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In this paper, a novel approach to high-level (i.e. architecture independent) worst case execution time (WCET) analysis is presented that automatically computes exact bounds for all inputs. To this end, we make use of the distinction between micro and macro steps as usually done by synchronous languages. As macro steps must not contain loops, a later low-level WCET analysis (architecture dependent) is simplified to a large extent. Checking exact execution times for all inputs is a complex task that can nevertheless be efficiently done when implicit state space representations are used. With our tools, it is not only possible to compute path information by exploring all computations, but also to verify given path information.