On the development of reactive systems
Logics and models of concurrent systems
Static timing analysis of embedded software
DAC '97 Proceedings of the 34th annual Design Automation Conference
Proof, language, and interaction
Guest Editorial: A Review of Worst-Case Execution-TimeAnalysis
Real-Time Systems - Special issue on worst-case execution-time analysis
Static Worst-Case Execution Time Analysis of Synchronous Programs
Ada-Europe '00 Proceedings of the 5th Ada-Europe International Conference on Reliable Software Technologies
Constructive Analysis of Cyclic Circuits
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Towards direct execution of esterel programs on reactive processors
Proceedings of the 4th ACM international conference on Embedded software
Exact High Level WCET Analysis of Synchronous Programs by Symbolic State Space Exploration
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An Esterel processor with full preemption support and its worst case reaction time analysis
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Optimization for faster execution of Esterel programs
Formal methods and models for system design
A concurrent reactive Esterel processor based on multi-threading
Proceedings of the 2006 ACM symposium on Applied computing
Mapping esterel onto a multi-threaded embedded processor
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Compiling Esterel
Instantaneous termination in pure Esterel
SAS'03 Proceedings of the 10th international conference on Static analysis
Predicting computation time for advanced processor architectures
Euromicro-RTS'00 Proceedings of the 12th Euromicro conference on Real-time systems
Approximate reachability for dead code elimination in esterel
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
An Esterel compiler for large control-dominated systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Building timing predictable embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
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The recently proposed reactive processing architectures are characterized by instruction set architectures (ISAs) that directly support reactive control fow including concurrency and preemption. These architectures provide efficient execution platforms for reactive synchronous programs; however, they do require novel compiler technologies, notably with respect to the handling of concurrency. Another key quality of the reactive architectures is that they have very predictable timing properties, which make it feasible to analyze their worst-case reaction time (WCRT). We present an approach to compile programs written in the synchronous language Esterel onto a reactive processing architecture that handles concurrency via priority-based multithreading. Building on this compilation approach, we also present a procedure for statically determining tight, safe upper bounds on the WCRT. Experimental results indicate the practicality of this approach, withWCRT estimates to be accurate within 22% on average.