The ESTEREL synchronous programming language: design, semantics, implementation
Science of Computer Programming
Modeling hierarchical combinational circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Synchronous Programming of Reactive Systems
Synchronous Programming of Reactive Systems
The Denotational Description of Programming Languages: An Introduction
The Denotational Description of Programming Languages: An Introduction
Verification of Synchronous Sequential Machines Based on Symbolic Execution
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
BDD-Based Debugging Of Design Using Language Containment and Fair CTL
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Latch optimization in circuits generated from high-level descriptions
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
The maximal VHDL subset with a cycle-level abstraction
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Quick conservative causality analysis
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Efficient latch optimization using exclusive sets
DAC '97 Proceedings of the 34th annual Design Automation Conference
The Synchronous Approach to Designing Reactive Systems
Formal Methods in System Design - Special issue: industrial critical systems
Compiling Esterel into sequential code
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Compiling Esterel into sequential code
Proceedings of the 37th Annual Design Automation Conference
An Implementation of Constructive Synchronous Programs in POLIS
Formal Methods in System Design
A new method for compiling schizophrenic synchronous programs
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Design of embedded systems: formal models, validation, and synthesis
Readings in hardware/software co-design
IEEE Transactions on Software Engineering
Modular Causality in a Synchronous Stream Language
ESOP '01 Proceedings of the 10th European Symposium on Programming Languages and Systems
Proving the Equivalence of Microstep and Macrostep Semantics
TPHOLs '02 Proceedings of the 15th International Conference on Theorem Proving in Higher Order Logics
On the Combination of Synchronous Languages
COMPOS'97 Revised Lectures from the International Symposium on Compositionality: The Significant Difference
Synchronous Modelling of Asynchronous Systems
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Automatic Production of Globally Asynchronous Locally Synchronous Systems
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Stability of Discrete Sampled Systems
FTRTFT '00 Proceedings of the 6th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems
Compositional Verification of Synchronous Networks
FTRTFT '00 Proceedings of the 6th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems
Cronos: A Separate Compilation Toolset for Modular Esterel Applications
FM '99 Proceedings of the Wold Congress on Formal Methods in the Development of Computing Systems-Volume II
Efficient Analysis of Cyclic Definitions
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Tutorial: Compiling concurrent languages for sequential processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Making cyclic circuits acyclic
Proceedings of the 40th annual Design Automation Conference
The semantics and execution of a synchronous block-diagram language
Science of Computer Programming
On breakable cyclic definitions
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
ACM Transactions on Embedded Computing Systems (TECS)
An efficient combinationality check technique for the synthesis of cyclic combinational circuits
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Acyclic modeling of combinational loops
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Optimization for faster execution of Esterel programs
Formal methods and models for system design
Formal Reasoning About Causality Analysis
TPHOLs '08 Proceedings of the 21st International Conference on Theorem Proving in Higher Order Logics
Modular code generation from synchronous block diagrams: modularity vs. code size
Proceedings of the 36th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Challenges in the Specification of Full Contracts
IFM '09 Proceedings of the 7th International Conference on Integrated Formal Methods
Automated abstraction by incremental refinement in interpolant-based model checking
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Compilation and worst-case reaction time analysis for multithreaded Esterel processing
EURASIP Journal on Embedded Systems - Model-driven high-level programming of embedded systems: selected papers from SLA++P'07 and SLA++P'08
Embedded systems programming: accessing databases from Esterel
EURASIP Journal on Embedded Systems - Model-driven high-level programming of embedded systems: selected papers from SLA++P'07 and SLA++P'08
Electronic Notes in Theoretical Computer Science (ENTCS)
Safety Property Verification of Cyclic Synchronous Circuits
Electronic Notes in Theoretical Computer Science (ENTCS)
A Verified Compiler for Synchronous Programs with Local Declarations
Electronic Notes in Theoretical Computer Science (ENTCS)
Journal of Electronic Testing: Theory and Applications
Efficient simulation of oscillatory combinational loops
Proceedings of the 47th Design Automation Conference
Constructive semantics for instantaneous reactions
Theoretical Computer Science
Approximate reachability for dead code elimination in esterel
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
Argos: an automaton-based synchronous language
Computer Languages
Constructive Boolean circuits and the exactness of timed ternary simulation
Formal Methods in System Design
Applying Techniques of Asynchronous Concurrency to Synchronous Languages
Fundamenta Informaticae
Formal semantics of modular time refinement in AutoFocus
Computer Science - Research and Development
Proceedings of the Conference on Design, Automation and Test in Europe
Synchronous digital circuits as functional programs
ACM Computing Surveys (CSUR)
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Traditionally, circuits with combinational loops are found only in asynchronous designs. However, combinational loops can also be useful for synchronous circuit design. Combinational loops can arise from high-level language behavioral compiling, and can be used to reduce circuit size. We provide a symbolic algorithm that detects if a sequential circuit with combinational loops exhibits standard synchronous behavior, and if so, produces an equivalent circuit without combinational loops. We present applications to hardware and software synthesis from the Esterel synchronous programming language.