The ESTEREL synchronous programming language: design, semantics, implementation
Science of Computer Programming
Analysis of cyclic combinational circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
False loops through resource sharing
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Constructive Analysis of Cyclic Circuits
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Formal analysis of synchronous circuits
Formal analysis of synchronous circuits
A Verified Compiler for Synchronous Programs with Local Declarations
Electronic Notes in Theoretical Computer Science (ENTCS)
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The causality problem is that of determining if a combinational circuit with cycles has acceptable behavior: that for all inputs the outputs are well defined and stable. While the problem manifests itself at the circuit level, it usually originates at the system level. It may arise when a system is designed as a collection of modules: when composed, cycles are discovered in the ensemble. One must analyze these cycles to correct possible errors or to capture the correct behavior appropriately for further synthesis. Previously published algorithms use iterated ternary logic simulation. This is correct and robust, but expensive and in many cases overkill. We propose a more efficient but conservative algorithm based on applying standard logic synthesis techniques of increasing power. We present initial results to demonstrate the practicality of this approach.