Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
False loops through resource sharing
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications
Verity—a formal verification program for custom CMOS circuits
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Extracting RTL models from transistor netlists
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
The maximal VHDL subset with a cycle-level abstraction
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Quick conservative causality analysis
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Timing Analysis of Combinational Circuits in Intuitionistic Propositional Logic
Formal Methods in System Design
Automated equivalence checking of switch level circuits
Proceedings of the 39th annual Design Automation Conference
Synchronous Modelling of Asynchronous Systems
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Stability of Discrete Sampled Systems
FTRTFT '00 Proceedings of the 6th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems
Efficient Analysis of Cyclic Definitions
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Extracting Exact Time Bounds from Logical Proofs
LOPSTR '01 Selected papers from the 11th International Workshop on Logic Based Program Synthesis and Transformation
An integrated environment for HDL verification
IVC '95 Proceedings of the 4th IEEE International Verilog HDL Conference
The semantics and execution of a synchronous block-diagram language
Science of Computer Programming
ACM Transactions on Embedded Computing Systems (TECS)
A deterministic logical semantics for pure Esterel
ACM Transactions on Programming Languages and Systems (TOPLAS)
Bounded model checking of infinite state systems
Formal Methods in System Design
A Deterministic Logical Semantics for Esterel
Electronic Notes in Theoretical Computer Science (ENTCS)
Approximate reachability for dead code elimination in esterel
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
Dependable polygon-processing algorithms for safety-critical embedded systems
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
Ternary simulation: refinement of binary functions or abstraction of real-time behaviour?
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
On the asymptotic costs of multiplexer-based reconfigurability
Proceedings of the 49th Annual Design Automation Conference
Synchronous digital circuits as functional programs
ACM Computing Surveys (CSUR)
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