Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Analysis of cyclic combinational circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Comparing layouts with HDL models: a formal verification technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On Efficiently Producing Quality Tests forCustom Circuits in PowerPC™ Microprocessors
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
An improved hierarchical classification algorithm for structural analysis of integrated circuits
Proceedings of the conference on Design, automation and test in Europe
Validating PowerPC Microprocessor Custom Memories
IEEE Design & Test
Formal Verification of Combinational Circuit
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Using ATPG for clock rules checking in complex scan designs
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Tradeoff Analysis For Producing High Quality Tests For Custom Circuits in PowerPCTM Microprocessors
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
This paper addresses the problem of deriving a register-transfer level (RTL) model from a transistor-level circuit. Using existing techniques, the transistor-level circuit is converted into a relation that describes the evolution of the signals in the circuit with respect to the simulator clock. This simulation relation is then manipulated to derive the stable behavior of the circuit. Given this stable behavior and information about the clocking scheme, we determine if the circuit is combinational, asynchronous or synchronous. For combinational and synchronous circuits we derive an equivalent register-transfer level model. This development enables full-custom circuit designers to use tools that were till now available only to designers working at the gate-level. The algorithm has been successfully used to characterize several custom designs, as well as the entire AT&T standard-cell library.