Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Verifying a static RAM design by logic simulation
Proceedings of the fifth MIT conference on Advanced research in VLSI
Synchronous circuit verification by symbolic simulation: an illustration
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
Extracting RTL models from transistor netlists
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Formal verification of PowerPC arrays using symbolic trajectory evaluation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
DAC '98 Proceedings of the 35th annual Design Automation Conference
Formal Verification of Digital Circuits Using Symbolic Ternary System Models
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
PowerPCTM Array Verification Methodology using Formal Techniques
Proceedings of the IEEE International Test Conference on Test and Design Validity
Symbolic simulation for correct machine design
DAC '79 Proceedings of the 16th Design Automation Conference
The application of program verification techniques to hardware verification
DAC '79 Proceedings of the 16th Design Automation Conference
Validation of PowerPC(tm) Custom Memories using Symbolic Simulation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
VOSS - A Formal Hardware Verification System User''s Guide
VOSS - A Formal Hardware Verification System User''s Guide
Comparing layouts with HDL models: a formal verification technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design and Development Paradigm for Industrial Formal Verification CAD Tools
IEEE Design & Test
Formal Verification Successes at Motorola
Formal Methods in System Design
Using Abstract Specifications to Verify PowerPCTM Custom Memories by Symbolic Trajectory Evaluation
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Enhanced symbolic simulation for efficient verification of embedded array systems
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Formal Methods in System Design
Error Diagnosis in Equivalence Checking of High Performance Microprocessors
Electronic Notes in Theoretical Computer Science (ENTCS)
| Hi-index | 0.00 |
Due to the high cost of correcting errors in a final product, there is a growing impetus in the industry towards methodologies that can yield correct designs in the first manufacturing run. Design validation methodologies that combine simulation techniques with formal reasoning can be effective in ensuring correct operation of software and hardware systems. We present a validation methodology for PowerPC custom memories based on symbolic simulation and present results on an industrial project at Somerset. We also show why simulation is necessary to complement formal mathematical reasoning in verifying certain classes of custom designed circuits. We then present our results and outline our goals in the areas of design validation using symbolic simulation.