Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
Formal verification of PowerPC arrays using symbolic trajectory evaluation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Validating PowerPC Microprocessor Custom Memories
IEEE Design & Test
Formal Verification of Digital Circuits Using Symbolic Ternary System Models
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
PowerPCTM Array Verification Methodology using Formal Techniques
Proceedings of the IEEE International Test Conference on Test and Design Validity
Automatic verification of safety and liveness for pipelined machines using WEB refinement
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Formal tools are either too labor intensive or are completely impractical for industrial-size problems. This paper describes two formal verification tools used within Motorola, Versys2 and CBV, that challenge this assertion. The two tools are being used in current design verification flows and have shown that it is possible to seamlessly integrate formal tools into existing design flows.