Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
The formal verification of a pipelined double-precision IEEE floating-point multiplier
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Formal verification of PowerPC arrays using symbolic trajectory evaluation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Formal verification of content addressable memories using symbolic trajectory evaluation
DAC '97 Proceedings of the 34th annual Design Automation Conference
DAC '98 Proceedings of the 35th annual Design Automation Conference
Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques
Proceedings of the 37th Annual Design Automation Conference
Reliable verification using symbolic simulation with scalar values
Proceedings of the 37th Annual Design Automation Conference
Experience in Validation of PowerPCTM Microprocessor Embedded Arrays
Journal of Electronic Testing: Theory and Applications
Validating PowerPC Microprocessor Custom Memories
IEEE Design & Test
Symbolic Simulation with Approximate Values
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems
ITC '02 Proceedings of the 2002 IEEE International Test Conference
VOSS - A Formal Hardware Verification System User''s Guide
VOSS - A Formal Hardware Verification System User''s Guide
A simple theorem prover based on symbolic trajectory evaluation and BDD's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improved Symoblic Simulation by Dynamic Funtional Space Partitioning
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Improved symbolic simulation by functional-space decomposition
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In the past, Symbolic Trajectory Evaluation (STE) was shown to be effective for verifying individual array blocks. However, when applying STE to verify multiple array blocks together as a single system, the run-time OBDD sizes would often blow up. In this paper, we propose using a "dual-rail" symbolic simulation scheme to facilitate the application of STE proof methodology for verifying array systems. The proposed scheme implicitly partitions a given design into control domain and data-path domain, and symbolic simulation is carried out on both domains. With this scheme, the run-time OBDD sizes during the symbolic simulation for each domain can be limited. We demonstrate the effectiveness of our approach by verifying the Memory Management Unit (MMU) in Motorola high-performance microprocessors. The verification of MMU as a whole was not possible before because of the OBDD size blow-up problem when an ordinary symbolic simulator was used in the STE proof process.