Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Formal verification using parametric representations of Boolean constraints
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Digital Systems Design with VHDL and Synthesis
Digital Systems Design with VHDL and Synthesis
Verification of Floating-Point Adders
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Improved symbolic simulation by functional-space decomposition
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Enhanced symbolic simulation for efficient verification of embedded array systems
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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In this paper, we provide a flexible and automatic method to partition the functional space for efficient symbolic simulation. We utilize a 2-tuple list representation as the basis for partitioning the functional space. The partitioning is carried out dynamically during the symbolic simulation based on the sizes of OBDDs. We develop heuristics for choosing the optimal partitioning points. These heuristics intend to balance the tradeoff between the time and space complexity. We demonstrate the effectiveness of our new symbolic simulation approach through experiments based on a floating point adder and a memory management unit.