Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
Combining theorem proving and trajectory evaluation in an industrial environment
DAC '98 Proceedings of the 35th annual Design Automation Conference
Verification of Floating-Point Adders
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Symbolic Trajectory Evaluation
Formal Hardware Verification - Methods and Systems in Comparison
Formal verification of iterative algorithms in microprocessors
Proceedings of the 37th Annual Design Automation Conference
A hybrid verification approach: getting deep into the design
Proceedings of the 39th annual Design Automation Conference
Practical Formal Verification in Microprocessor Design
IEEE Design & Test
Verifying the Implementation of an Error Control Code
Formal Methods in System Design
A Methodology for Large-Scale Hardware Verification
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Sequential Equivalence Checking by Symbolic Simulation
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Symbolic Simulation with Approximate Values
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Simplifying Circuits for Formal Verification Using Parametric Representation
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Abstraction by Symbolic Indexing Transformations
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Generalized Symbolic Trajectory Evaluation - Abstraction in Action
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Lifted-FL: A Pragmatic Implementation of Combined Model Checking and Theorem Proving
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
Xs are for Trajectory Evaluation, Booleans are for Theorem Proving
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Applications of Hierarchical Verification in Model Checking
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Combinational equivalence checking through function transformation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Improved SAT-based Bounded Reachability Analysis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Introduction to generalized symbolic trajectory evaluation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Improved Symoblic Simulation by Dynamic Funtional Space Partitioning
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A SAT-based algorithm for reparameterization in symbolic simulation
Proceedings of the 41st annual Design Automation Conference
Improved symbolic simulation by functional-space decomposition
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Set Manipulation with Boolean Functional Vectors for Symbolic Reachability Analysis
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Verification of Boolean programs with unbounded thread creation
Theoretical Computer Science
Centaur Technology Media Unit Verification
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Challenges for formal verification in industrial setting
FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology
Symbolic model checking for asynchronous boolean programs
SPIN'05 Proceedings of the 12th international conference on Model Checking Software
Efficient symbolic simulation via dynamic scheduling, don't caring, and case splitting
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Exploiting constraints in transformation-based verification
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
A mechanically verified AIG-to-BDD conversion algorithm
ITP'10 Proceedings of the First international conference on Interactive Theorem Proving
| Hi-index | 0.00 |