Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Formal verification using parametric representations of Boolean constraints
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Digital Systems Design with VHDL and Synthesis
Digital Systems Design with VHDL and Synthesis
Verification of Floating-Point Adders
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Enhanced symbolic simulation for efficient verification of embedded array systems
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Improved Symoblic Simulation by Dynamic Funtional Space Partitioning
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper presents a functional-space decomposition approach to enhance the capability of symbolic simulation. In our symbolic simulator, the control part and data path of a circuit is separated, and their simulated results are recorded in different domains. A 2-tuple list structure is used to separate the results in the control and datapath domains. Then, the functional sub-space in the control domain can further be decomposed in order to achieve the optimal OBDD size and run time. We demonstrate the effectiveness of our decomposition approach based on symbolic simulation of arithmetic circuit units.