Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
Formal verification using parametric representations of Boolean constraints
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Circuit-based Boolean Reasoning
Proceedings of the 38th annual Design Automation Conference
Computer-Aided Reasoning: An Approach
Computer-Aided Reasoning: An Approach
Abstraction by Symbolic Indexing Transformations
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Symbolic Trajectory Evaluation
Formal Hardware Verification - Methods and Systems in Comparison
Function memoization and unique object representation for ACL2 functions
ACL2 '06 Proceedings of the sixth international workshop on the ACL2 theorem prover and its applications
Centaur Technology Media Unit Verification
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
An industrially effective environment for formal hardware verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We present the mechanical verification of an algorithm for building a BDD from an AND/INVERTER graph (AIG). The algorithm uses two methods to simplify an input AIG using BDDs of limited size; it repeatedly applies these methods while varying the BDD size limit. One method is similar to dynamic weakening in that it replaces oversized BDDs by a conservative approximation; the other method introduces fresh variables to represent oversized BDDs. This algorithm is written in the executable logic of the ACL2 theorem prover. The primary contribution is the verification of our conversion algorithm. We state its correctness theorem and outline the major steps needed to prove it.