Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
Tight integration of combinational verification methods
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
A Computing Procedure for Quantification Theory
Journal of the ACM (JACM)
Novel verification framework combining structural and OBDD methods in a synthesis environment
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A Small Test Generator for Large Designs
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Equivalence checking of combinational circuits using Boolean expression diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SAT with partial clauses and back-leaps
Proceedings of the 39th annual Design Automation Conference
Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver
Proceedings of the 39th annual Design Automation Conference
Combinational and sequential equivalence checking
Logic Synthesis and Verification
The future of logic synthesis and verification
Logic Synthesis and Verification
Min-area retiming on flexible circuit structures
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Transformation-Based Verification Using Generalized Retiming
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Property Checking via Structural Analysis
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
SAT and ATPG: Boolean engines for formal hardware verification
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A signal correlation guided ATPG solver and its applications for solving difficult industrial cases
Proceedings of the 40th annual Design Automation Conference
Learning from BDDs in SAT-based bounded model checking
Proceedings of the 40th annual Design Automation Conference
Improved SAT-based Bounded Reachability Analysis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Enhanced Diameter Bounding via Structural
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Managing Don't Cares in Boolean Satisfiability
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Using Word-Level Information in Formal Hardware Verification
Automation and Remote Control
Iterative Abstraction using SAT-based BMC with Proof Analysis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Efficient translation of boolean formulas to CNF in formal verification of microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A Circuit SAT Solver With Signal Correlation Guided Learning
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model Checking
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Considering Circuit Observability Don't Cares in CNF Satisfiability
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Unrestricted vs restricted cut in a tableau method for Boolean circuits
Annals of Mathematics and Artificial Intelligence
DAG-aware circuit compression for formal verification
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Efficient SAT-based unbounded symbolic model checking using circuit cofactoring
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
BDD-based verification of scalable designs
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
RTL SAT simplification by Boolean and interval arithmetic reasoning
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Kauffman networks: analysis and applications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Scalable compositional minimization via static analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
QuteSAT: a robust circuit-based SAT solver for complex circuit structure
Proceedings of the conference on Design, automation and test in Europe
Don't care words with an application to the automata-based approach for real addition
Formal Methods in System Design
Justification-Based Local Search with Adaptive Noise Strategies
LPAR '08 Proceedings of the 15th International Conference on Logic for Programming, Artificial Intelligence, and Reasoning
Justification-Based Non-Clausal Local Search for SAT
Proceedings of the 2008 conference on ECAI 2008: 18th European Conference on Artificial Intelligence
Hybrid BDD and All-SAT Method for Model Checking
Languages: From Formal to Natural
On the power of top-down branching heuristics
AAAI'08 Proceedings of the 23rd national conference on Artificial intelligence - Volume 1
An Incremental Algorithm to Check Satisfiability for Bounded Model Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Partitioning interpolant-based verification for effective unbounded model checking
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An AIG-Based QBF-solver using SAT for preprocessing
Proceedings of the 47th Design Automation Conference
Exploiting structure in an AIG based QBF solver
Proceedings of the Conference on Design, Automation and Test in Europe
Sechecker: a sequential equivalence checking framework based on K th invariants
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Transformations into normal forms for quantified circuits
SAT'11 Proceedings of the 14th international conference on Theory and application of satisfiability testing
Benchmarking a model checker for algorithmic improvements and tuning for performance
Formal Methods in System Design
CirCUs: a hybrid satisfiability solver
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Efficient conflict analysis for finding all satisfying assignments of a boolean circuit
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
DiVer: SAT-based model checking platform for verifying large scale systems
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Improved local search for circuit satisfiability
SAT'10 Proceedings of the 13th international conference on Theory and Applications of Satisfiability Testing
SAT-Based verification methods and applications in hardware verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
A mechanically verified AIG-to-BDD conversion algorithm
ITP'10 Proceedings of the First international conference on Interactive Theorem Proving
Simultaneous SAT-Based model checking of safety properties
HVC'05 Proceedings of the First Haifa international conference on Hardware and Software Verification and Testing
Optimization techniques for craig interpolant compaction in unbounded model checking
Proceedings of the Conference on Design, Automation and Test in Europe
Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits
Journal of Electronic Testing: Theory and Applications
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Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuit structures. Traditionally, canonical representations, e. g., BDDs, or SAT- based search methods are used to solve a particular class of problems. In this paper we present a combination of techniques for Boolean reasoning based on BDDs, structural transformations, and a SAT procedure natively working on a shared graph representation of the problem. The described intertwined integration of the three techniques results in a robust summation of their orthogonal strengths. Our experiments demonstrate the effectiveness of the approach.