Tight integration of combinational verification methods
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Boolean satisfiability in electronic design automation
Proceedings of the 37th Annual Design Automation Conference
Combinational equivalence checking using Boolean satisfiability and binary decision diagrams
Proceedings of the conference on Design, automation and test in Europe
Circuit-based Boolean Reasoning
Proceedings of the 38th annual Design Automation Conference
Dynamic detection and removal of inactive clauses in SAT with application in image computation
Proceedings of the 38th annual Design Automation Conference
Combinational and sequential equivalence checking
Logic Synthesis and Verification
Partition-based decision heuristics for image computation using SAT and BDDs
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
SAT-Based Image Computation with Application in Reachability Analysis
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
On a Model-Based Design Verificationfor Combinatorial Boolean Networks
IEA/AIE '02 Proceedings of the 15th international conference on Industrial and engineering applications of artificial intelligence and expert systems: developments in applied artificial intelligence
Checking satisfiability of a conjunction of BDDs
Proceedings of the 40th annual Design Automation Conference
Learning from BDDs in SAT-based bounded model checking
Proceedings of the 40th annual Design Automation Conference
A satisfiability procedure for quantified boolean formulae
Discrete Applied Mathematics - The renesse issue on satisfiability
Integrating CNF and BDD based SAT solvers
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
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There has been much interest in techniques which combine the advantages of function-based methods, such as BDDs, with structure-based methods, such as ATPG, for verifying the equivalence of combinational circuits. However, most existing efforts have focused on exploiting circuit similarity through use of learning and/or ATPG-based methods rather than on making the integration between BDDs and ATPG techniques efficient. This paper presents a new technique, where the focus is on improving the equivalence check itself, thereby making it more robust in the absence of circuit similarity. It is based on tight integration of a Boolean Satisfiability Checker with BDDs, whereby BDDs are effectively used to reduce both the problem size and the number of backtracks for the satisfiability problem. This methodology does not preclude exploitation of circuit similarity, when it exists, since the improved check can be easily incorporated as the inner loop of the well-known iterative framework involving search and replacement of internally equivalent nodes. We demonstrate the significance of our contributions with practical results on the ISCAS benchmark circuits.